KR940008263B1 - Noise decrease type ccd structure - Google Patents
Noise decrease type ccd structure Download PDFInfo
- Publication number
- KR940008263B1 KR940008263B1 KR1019910014042A KR910014042A KR940008263B1 KR 940008263 B1 KR940008263 B1 KR 940008263B1 KR 1019910014042 A KR1019910014042 A KR 1019910014042A KR 910014042 A KR910014042 A KR 910014042A KR 940008263 B1 KR940008263 B1 KR 940008263B1
- Authority
- KR
- South Korea
- Prior art keywords
- bccd
- type
- potential barrier
- gate oxide
- potential
- Prior art date
Links
- 238000005036 potential barrier Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims 2
- 150000002500 ions Chemical class 0.000 abstract description 5
- 238000002513 implantation Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
Abstract
Description
제1도는 종래의 CCD 구조 단면도.1 is a cross-sectional view of a conventional CCD structure.
제2도는 제1도의 A-A'선으로 본 포텐셜 종단면도.FIG. 2 is a potential longitudinal cross-sectional view taken along line AA ′ of FIG. 1.
제3도는 본 발명의 CCD 구조 단면도.3 is a cross-sectional view of a CCD structure of the present invention.
제 4 도는 제 3 도의 B-B'선으로 본 포텐셜 종단면도.4 is a potential longitudinal cross-sectional view taken along line B-B 'of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : n형 기판 2 : p웰1: n-type substrate 2: p-well
3 : BCCD 4 : 제 1 포텐셜 장벽3: BCCD 4: first potential barrier
5 : 제 2 포텐셜 장벽 6 : 폴리게이트5: second potential barrier 6: polygate
7 : 게이트 산화막7: gate oxide film
본 발명은 CCD 구조에 관한 것으로 특히 노이즈(noise) 감소에 적당하도록 표면에 포텐셜 장벽(Potential Barrier)을 형성한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD structure, in which a potential barrier is formed on a surface to be suitable for noise reduction.
종래의 CCD채널은 제1도에 도시한 바와같이 n형 기판(1)에 p웰(2)을 형성하고 전자가 전달되는 채널부위를 n형 불순물 이온주입으로 BCCD(Bluk CCD)(3)를 형성하여 전자의 전달이 벌크(Bulk)에서 일어나도록 하였다. 그리고 게이트 산화막(7) 위에는 채널의 포텐셜을 변환시켜 전하를 이동시키기 위한 제 1, 제 2 폴리게이트(6)가 반복적으로 형성이 되어 있으며 제2폴리게이트 하측의 BCCD(3)에는 p형 이온주입으로 포텐셜 장벽(5)이 형성되어 있다. 이와같이 구성된 종래의 CCD의 동작은 아래와 같다.In the conventional CCD channel, as shown in FIG. 1, the p well 2 is formed on the n-type substrate 1, and BCCD (Bluk CCD) 3 is formed by implanting n-type impurity ions into the channel region through which electrons are transferred. Formed to allow electron transfer to occur in bulk. The first and second polygates 6 are repeatedly formed on the gate oxide film 7 to transfer the charge by converting the potential of the channel, and the p-type ion implantation is performed in the BCCD 3 under the second polygate. The potential barrier 5 is formed. The operation of the conventional CCD configured as described above is as follows.
즉, 제2도와 같이 전하전달의 액션이 일어나는 BCCD(3)는 표면 트랩(trap)에 의해 발생하는 노이즈를 감소시키기 위한 방법으로 쓰이고, n타입 BCCD와 p웰에 의해 형성되는 포텐셜 프로파일이 게이트 바이어스에 의해 영향을 받게 되는 원리를 이용하여 전하를 옆으로 이동시킨다. 그러나 이와같은 종래의 CCD 구조는 게이트 바이어스가 "로우"에서 "하이"로 바뀌면 포텐셜 프로파일이 제2도에서와 같이 변하게 되어 전하가 표면트랩이 발생할 확률이 커지게 되어 노이즈 발생원인으로 작용하게 된다. 이는 HCCD 채널이 긴리니어 이미지 센서(Linear Image Sensor)등에서 중요한 문제가 된다.That is, BCCD 3, in which charge transfer action occurs as shown in FIG. 2, is used as a method for reducing noise generated by surface trap, and the potential profile formed by n-type BCCD and p-well is gate biased. The charge is moved sideways using the principle that is affected by. However, in the conventional CCD structure, when the gate bias is changed from "low" to "high", the potential profile is changed as shown in FIG. 2, which causes the charge to increase the probability of surface trapping, which causes noise. This is an important problem for a linear image sensor such as a long HCCD channel.
본 발명은 이와같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 BCCD 구조의 표면에 이온주입으로 포텐셜 베리어를 형성하여 표면 트랩에 의해 발생하는 노이즈를 감소시키기 위한 것이다. 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 제3도와 제4도를 이용하여 보다 상세히 설명하면 아래와 같다.The present invention is to solve such a problem, an object of the present invention is to form a potential barrier by ion implantation on the surface of the BCCD structure to reduce the noise caused by the surface trap. An embodiment of the present invention for achieving the above object will be described in more detail with reference to FIGS. 3 and 4 below.
즉, 제3도와 같이 n형 기판(1)위에 p웰(2)을 형성하고 전자가 전달되는 채널부위에 n형 불순물이온주입하여 BCCD(3)를 형성하고, BCCD(3)의 표면에 p형 불순물이 온주입을 하여 제1 포텐셜 장벽(4)을 형성한다. 그리고 상기 BCCD(3)의 상측에 게이트 산화막(7)이 형성되고, 게이트 산화막(7)위에는 채널이 포텐셜을 변환시켜 전하를 이동시키기 위한 제1, 제2 폴리게이트(6)가 반복적으로 형성되어 있으며 제2폴리게이트 하측의 BCCD(3)에는 p형 불순물 이온 주입으로 제2 포텐셜 장벽(5)이 형성되어, 본 발명의 CCD 소자가 구성된다.That is, as shown in FIG. 3, p wells 2 are formed on the n-type substrate 1, n-type impurity ions are implanted in the channel region through which electrons are transferred to form BCCD 3, and p is formed on the surface of the BCCD 3. Type impurity is inject | poured and the 1st potential barrier 4 is formed. A gate oxide film 7 is formed on the BCCD 3, and first and second polygates 6 are formed on the gate oxide film 7 to transfer charges by converting a potential of the channel. The second potential barrier 5 is formed in the BCCD 3 under the second polygate by p-type impurity ion implantation, thereby forming the CCD device of the present invention.
상기와 같이 구성된 본 발명의 CCD의 포텐셜 프로파일은 제4도와 같이, 게이트 산화막(7)바로 밑에 제 1 포텐셜 장벽(4)이 형성되어 BCCD에서 이송되는 전하가 직접 표면에 트랩이 되는 것을 막을 수 있다. 이는 게이트 바이어스가 "하이"로 변화되면 그 변화가 커져 표면트랩의 확률은 훨씬 감소된다.The potential profile of the CCD according to the present invention configured as described above, as shown in FIG. 4, may form a first potential barrier 4 directly under the gate oxide film 7, thereby preventing charges transferred from the BCCD from being directly trapped on the surface. . This means that as the gate bias changes to "high", the change becomes larger and the probability of surface traps is much reduced.
이상에서 설명한 바와같이 본 발명은 긴 채널 CCD를 이용하는 소자에서 표면트랩에 의해 발생하는 노이즈를 감소시킴으로써 다이나믹 영역(Dynamic range)등을 향상시키는 효과가 있다.As described above, the present invention has the effect of improving the dynamic range by reducing the noise generated by the surface trap in the device using the long channel CCD.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910014042A KR940008263B1 (en) | 1991-08-14 | 1991-08-14 | Noise decrease type ccd structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910014042A KR940008263B1 (en) | 1991-08-14 | 1991-08-14 | Noise decrease type ccd structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930005227A KR930005227A (en) | 1993-03-23 |
| KR940008263B1 true KR940008263B1 (en) | 1994-09-09 |
Family
ID=19318591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910014042A KR940008263B1 (en) | 1991-08-14 | 1991-08-14 | Noise decrease type ccd structure |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940008263B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6051502A (en) * | 1997-10-20 | 2000-04-18 | Micron Technology, Inc. | Methods of forming conductive components and methods of forming conductive lines |
-
1991
- 1991-08-14 KR KR1019910014042A patent/KR940008263B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930005227A (en) | 1993-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3570733B2 (en) | Virtual phase frame interline transfer CCD image sensor | |
| KR970011376B1 (en) | Ccd type solid state image sensing device | |
| KR20060126377A (en) | Pixel with asymmetric transfer gate channel doping | |
| KR0130959B1 (en) | Solid state imaging device and method of manufacture therefor | |
| US6624453B2 (en) | Lateral overflow drain, anti-blooming structure for CCD devices having improved breakdown voltage | |
| JPH0240956A (en) | Solid-state image sensing device | |
| KR970024251A (en) | Amplified Solid State Imaging Device and Manufacturing Method Thereof | |
| EP0059547B1 (en) | Clock controlled anti-blooming for virtual phase ccd's | |
| KR940008263B1 (en) | Noise decrease type ccd structure | |
| US6794219B1 (en) | Method for creating a lateral overflow drain, anti-blooming structure in a charge coupled device | |
| US4945392A (en) | Static induction transistor and manufacturing method of the same | |
| KR930011473B1 (en) | Pseudo different shape ccd with short channel effect | |
| JP2644937B2 (en) | Solid-state imaging device and method of manufacturing the same | |
| KR930000914B1 (en) | Photodiode over flow drain repression method from ccd imaging sensor | |
| JPH08264747A (en) | Solid-state picturization device having container-lateral-side overflow-drain inplant,and its manufacture | |
| JPH08288492A (en) | Solid-state image pickup device and its manufacture | |
| KR100192391B1 (en) | Electronics carrier injection transistor | |
| KR0156166B1 (en) | Solid state image sensor | |
| KR100198622B1 (en) | Solid-state image sensing device and manufacturing method thereof | |
| KR100223931B1 (en) | Solid state image sensing device | |
| JP2586571B2 (en) | Solid-state imaging device | |
| KR100677045B1 (en) | Fabricating method of Image sensor | |
| KR0140634B1 (en) | The fabrication method of solid state image sensing device | |
| JPH0697416A (en) | Solid-state image sensing device and manufacture thereof | |
| KR940008027B1 (en) | Ccd solid state imager and fabricating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050824 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |