KR970011376B1 - Ccd type solid state image sensing device - Google Patents

Abstract

A charge coupled device comprising the first well(32), a photodiode area(35) of the first conductive type, the second well(39), a VCCD channel area(43), a transmission gate channel area(39') of the second conductive type, a channel stop area(41) of the second conductive type, an impurities area(45) of the second conductive type, a insulated film(33), a transmission gate electrode(44), a layer interval insulated film(46), and a light shielding film(47).

Description

CDD solid-state imaging device

1 is a cross-sectional view of a conventional CCD solid-state image pickup device.

FIG. 2 is a potential distribution along the line A-A 'of FIG.

3 is a potential distribution along the line A-A 'of FIG.

4 is a potential distribution along the line B-B 'of FIG. 1 (at the time of signal charge reading).

5 is a cross-sectional view of an improved conventional CCD solid-state image pickup device.

6 is a cross-sectional view of a CCD solid-state image pickup device according to an embodiment of the present invention.

7 is a potential distribution diagram (C signal accumulation) between C-C 'of FIG.

FIG. 8 is a potential distribution (at the time of signal charge reading) between C-C 'of FIG.

9 is a diagram showing a simulation result of the potential distribution between the photodiode and the VCCD channel region when the transfer gate is turned off in the solid-state image pickup device of the present invention.

FIG. 10 is a diagram showing simulation results of potential distribution between a photodiode and a VCCD channel region when the transfer gate is turned on in the solid state image pickup device of the present invention. FIG.

11 (A)-(I) are manufacturing process diagrams of the CCD solid-state image pickup device of FIG.

* Explanation of symbols for main parts of the drawings

31 silicon substrate 32 first well

33: insulating film 34, 36, 37, 38, 40, 42: photoresist film

35 photodiode region 39 second well

41: channel stop area 43: VCCD channel area

44: transmission gate 45: P layer

46: interlayer insulating film 47: light shielding film

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a solid state (CD) type CDC, and more particularly, to a solid state image pickup device having a buried transfer gate channel region and a rivet type photodiode region having a gradation concentration distribution.

1 is a cross-sectional view of a conventional interlace CDD solid-state image pickup device.

Conventional CCD solid-state image pickup devices have an n-type substrate 11, a P-type well 12 formed on the n-type substrate 11, and a P-type well at a depth of 0.5 to 0.7 mu m by ion implantation of n-type impurities. In order to reduce surface noise of the plurality of n-type photodiode regions 13 and n-type photodiode 13 formed on (12), a high concentration formed on the n-type photodiode 13 with a depth of 0.1-0.2 탆. P A plurality of n formed in the P-type well 13 at a depth of 0.3-0.7 탆 at a predetermined interval from the layer 14 and the n-type photodiode region 13 and serving as a vertical transmission channel for signal transmission. N in p-type well 12 formed between n-type VCCD channel 15 and n-type photodiode 13 in type VCCD (Ver-tical Charge Coupled Device) channel region 15 Insulating the p-type transfer gate channel region 16 formed between the VCCD channel 15 and the n-type photodiode 13 and the n-type photodiode region 13 and the n-type VCCD channel region 15 of the previous stage. P-type channel stop region 17 formed therebetween, thin film insulating film 18 formed over the entire surface of the substrate, p-type channel stop region 17, p-type transfer gate channel region 16, An opening 22 only in the transfer gate (TG) 19 formed on the n-type VCCD channel region 15 and made of a polysilicon film doped with n-type impurities, and the n-type photodiode region 13. As the interlayer insulating film 20 to insulate the metal light shielding film 21 and the metal light shielding film 21 and the transfer gate 19 selectively removed only in the n-type photodiode region 13 so that light is incident through Was done. The operation of a conventional CCD type solid-state imaging device having the above-described structure is an accumulation mode for accumulating signal charges generated in the n-type photodiode region 13 by light incident through the opening 22. mode) and a read out mode for transmitting the signal charges stored in the n-type photodiode region 13 to the n-type VCCD channel region 15. FIG.

The accumulation mode is an operation of collecting signal charges for a predetermined time in the IT method, and the potentials of the respective portions of the solid state image pickup device are distributed as shown in FIG.

Therefore, the signal charges generated by the incident light due to the potential barriers formed by the p-type transfer gate channel region 16 and the p-type well 12 are continuously moved in the n-type photodiode region 13 for a certain period of time. 60 ~ 1/30 second).

In the accumulation mode, a voltage of 0 volts is applied to the transfer gate 19 to accumulate in the p-type transfer gate channel region 16 and the n-type photodiode region 13 as shown in FIG. A certain potential barrier is formed to prevent the charge from being transferred.

On the other hand, the read mode is an operation for transferring the signal charges accumulated in the n-type photodiode region 13 to the n-type VCCD channel region 15, where the potential of each part of the solid state image pickup device is A-A in FIG. It is distributed as shown in FIG. 3 in the section along the line, and as shown in FIG. 4 in the section along the line BB in FIG.

In the accumulation mode, a voltage of about 15 volts is applied to the transfer gate 19, whereby the potential of the n-type VCCD channel region 15 is extremely low, and the potential of the p-type transfer gate channel region 16 is also lowered. As shown in FIG. 3 and FIG. Therefore, the signal charge accumulated in the photodiode region 13 moves to the n-type VCCD channel region 15 through the p-type transfer gate channel region 16, and the signal charge is read out.

In the conventional solid state device, since the signal charge accumulated in the n-type photodiode region 13 is transferred to the VCCD channel region 15 through the transfer gate channel region 16, the surface area of the transfer gate must be wide. In addition, there is a problem in that the probability of including the signal charge noise charge transmitted to the VCCD channel region 15 increases.

Further, since the junction depth of the photodiode region 13 is shallow, the sensitivity characteristic is not good, and thus the smear characteristic is not good.

In addition, when the width of the photodiode region 13 becomes wider, the image lag characteristic is not good because the surrounding field does not act greatly even when the transfer gate 19 is turned on.

In addition, when strong light is incident on the photodiode region 13 through the opening 22, the charge path for inducing surplus charge to the substrate 11 is narrowed, which results in a good blooming characteristic. The problem is that no.

5 is a cross-sectional view of a conventional solid-state imaging device having improved blooming characteristics, in which a second p-type well 23 is formed in the n-type VCCD channel region 15 and by implanting p-type impurities by high energy ion implantation. .

This is well described in ITEJ Technical Report Vol 16, No. 18, pp 7-12, IPU 92.8-92.9 (Feb, 1992).

However, a solid-state imaging device having a double well structure can improve the blooming characteristics in FIG. 1, but similar to that in FIG. 1, the solid-state image pickup device can be used for signal charge movement through a photodiode region and a transfer gate channel region with a shallow depth of integration. The problem caused by the system could not be solved.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a CCD solid state device for improving the sensitivity, signal delay, smear and noise characteristics, and defect characteristics generated during the manufacturing process.

In order to achieve the above object, the present invention provides a silicon substrate of a first conductive type, a first well of a second conductive type formed on a silicon substrate, and a plurality of first conductive parts formed wide and deep at a predetermined distance from each other in the first well. The second well and the second well of the second conductivity type formed in the first well by overlapping with the photodiode region of the type, the photodiode region, and the photodiode region of the previous stage adjacent to the phototiode region. A plurality of first conduction type VCCD channel regions and a photogate region and a second conduction transfer gate channel region formed in a second well between the VCCD channel region, the corresponding VCCD channel region and the previous photodiode Insulation of the second conductive type channel stop region formed in the second well for isolation between the area, the second conductive type impurity region formed under the surface of each photodiode region and the thin film formed on the front surface of the substrate. And a transfer gate electrode formed on the insulating film on the second well upper portion, a interlayer insulating film formed on the insulating film so as to surround the transfer gate electrode, and a light shielding film formed on the entire surface of the substrate except for each photodiode region. An imaging device is provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 6 shows a cross-sectional structure of a CCD solid-state image pickup device according to an embodiment of the present invention.

Referring to FIG. 6, in the CCD type solid-state image pickup device of the present invention, a p-type well 32 is formed on an n-type substrate 31, and an n-type photodiode region is formed in the p-type well 32. . The n-type photodiode region 35 includes a relatively high concentration photodiode photodiode region 35-3, a medium concentration photodiode region 35-2, and a relatively low concentration photodiode photodiode region ( 35-1), and the concentration distribution of impurities is not constant over the entire region, but has a concentration distribution in which the impurity concentration is gradually lowered from the VCCD channel region 43.

And, on the n-type photodiode region 35, high concentration p for reducing surface noise Layer 45 is formed.

In addition, among the n-type photodiode regions 35 adjacent to each other, that is, among the n-type photo-tiode regions 35 'and the high-density and photo-tides 35-3 and the front-end n-type phototides 35'. A second p well 39 overlapped with these is formed between the low concentration photodiodes 35'-1, and the n-type VCCD channel region 43 and the p-type transfer gate channel are formed in the second p well 39. A region 39 'and a p-type channel stop region 41 were formed.

The p-type channel stop region 41 serves to separate the low concentration phototides 35-1 and the n-type VCCD channel region 43 out of the n-type phototides region 35 'at the front end.

The p-type transfer gate channel region 39 ′ is formed between the high concentration photodiode 35-3 of the n-type photodiode region 35 and the n-type VCCD channel region 43.

An insulating film 33 of a thin film such as an oxide film is formed on the entire surface of the substrate 31, and the p-type channel stop region 41, the n-type VCCD channel region 43, and the p-type transfer gate channel region are formed on the insulating film 33. A transfer gate 44 is formed over the 39 ', and a light shielding layer 47 made of metal is formed on the entire surface of the substrate except for the upper side of the photodiode region 35, and the light shielding layer 47 and the transmission are formed. An interlayer insulating film 46 for insulating the gates 44 was formed therebetween.

In the solid state image pickup device, the second p-type well 39 p The mold layer 45 has a higher impurity concentration than the photodiode region 35, the p-type transfer gate channel region 39 'has a lower impurity concentration than the channel stop region 41, and the photodiode region 35 Impurity concentration is higher than that of the first p-type well 32. The operation of the solid state image pickup device having the above structure will be described with reference to FIGS.

First, the operation in the accumulation mode will be described with reference to FIG. 7 in which the potential distribution between B-B 'in FIG. 6 is shown. Referring to FIG. 7, in the accumulation mode, since the concentration distribution of the photodiode region 35 is different for each position, the pinch off potential is formed differently, and thus, in the transmission gate channel region 39 ′, The peak of dislocation is also deeply formed (about 1.2 mu m to 1.7 mu m) toward the bulk side.

Therefore, the intensity characteristic of the red wavelength band becomes very good.

In addition, since the potentials are distributed stepwise in the photodiode region 35, a small amount of charge is first moved to and accumulated in the portion 35-3 having the highest concentration in the photodiode region 35.

Therefore, it is possible to read easily into the VCCD channel region 43 when the transfer gate 44 is turned on. Next, the operation in the read mode will be described.

When a voltage of about 15 V is applied to the transfer gate 44 and turned on, the potential is distributed as shown in FIG. 8, and charges accumulated in the n-type photodiode region 35 are transferred to the bulk gate channel region 39 ′. Is moved to and read from the n-type VCCD channel region 43 through e.

At this time, the accumulated signal charge is moved to the bulk side rather than the surface of the transfer gate channel region 39 'due to the presence of the high concentration of the second p-type well 39, thereby reading complete signal charge unaffected by noise. Therefore, the signal delay characteristic is improved.

Since the photodiode region 35 is wide and deep, the charge path for spreading the surplus charge onto the n-type substrate 31 when the surplus charge is present in the photodiode region 35 is much wider than that of the conventional structure. Therefore, the effect by side diffusion becomes small.

Thus, the anti-blooming characteristic is improved.

9 and 10 show simulation result values of the potential distribution of the photodiode region 35 and the VCCD channel region 43 in the solid state image pickup apparatus of the present invention. FIG. 10 shows potential distribution diagrams when 15V is applied to the transfer gate 44 and turned on, respectively.

11 (A)-(I) show a manufacturing process diagram of the solid state image pickup device according to the embodiment of the present invention.

Referring to FIG. 11A, the p-type epitaxial layer is formed on the n-type silicon substrate 31 or the p-type impurities are ion implanted and thermally diffused to form the first p-type wells 3 to 6 μm. Form to thickness. The n-type silicon substrate 31 has a resistance value of 10 to 200 Pa · cm. A thin film oxide film 33 is formed on the first p-type well 32 as an insulating film. A nitride film may be used instead of the oxide film as the insulating film.

11B and 11D are process charts for forming n-type phototides.

First, as shown in FIG. 11 (B), the photoresist film 34 is coated on the oxide film 33 and patterned to expose the oxide film 33 in the portion where the photodiode is to be formed. An n-type impurity is ion-implanted into the first p-type well 32 through the exposed oxide layer 33 to form a relatively low concentration n-type photodiode 35-1.

Subsequently, as shown in FIG. 11C, the photoresist film 34 is removed, the photoresist film 36 is applied again, and patterned to form an oxide film 33 on the low concentration n-type photodiode 35-1. Expose some

N-type impurities are ion-implanted into the low-concentration n-type photodiode 35-1 through the exposed oxide layer 33, so that the concentration of n is relatively higher than that of the low-concentration n-type photodiode 35-1. The photodiode 35-2 is formed.

As shown in FIG. 11D, the photoresist film 36 is removed, and a new photodiode film 37 is applied and patterned to form an oxide film 33 on an intermediate concentration n-type photodiode 35-2. ) Expose some.

N-type impurities are implanted into the medium-type n-type photodiode 35-2 through the exposed oxide film 33, so that the high-density concentration is higher than that of the medium-type n-type photodiode 35-2. An n-type photodiode 35-3 is formed.

As described above, by performing a selective photolithography process, the n-type impurities are ion implanted at different concentrations according to positions, and thermally diffused to form n-type photodiode regions 35 having a stepped concentration distribution according to positions. To form.

The photodiode region 35 has a junction depth of about 1.5 to 3.5 μm and has a higher impurity concentration than the first p-type well 32.

Referring to FIG. 11E, the photoresist film 37 is removed, a new photoresist film 38 is applied, and patterned to form an oxide film 33 and a photodiode region between the photodiode regions 35. A portion of the oxide film 33 on the 35 is exposed. A high concentration of p-type impurities are ion-implanted and thermally crushed through the exposed oxide film 33 to form a second p-type well 39. The second p-type well 39 has a high concentration of n-type phototides 35-3 and a low concentration of n-type phototides 35 'among phototides adjacent to the high concentration of n-type phototides 35-3. It is formed so as to overlap these areas between -1). The second p-type well 39 has a higher impurity concentration than the n-type photodiode region 35, and has a junction depth of about 1.0 to 1.5 μm.

Referring to FIG. 11 (G), the photoresist film 38 is removed, the photoresist film 40 is applied and patterned again, and the second p-type well overlapped with the low concentration photodiode 35-1. The oxide film 33 on the 39 is partially exposed. P-type impurities are ion-implanted into the second p-type well 39 through the exposed oxide film 33 to form a high concentration of the p-type channel stop region 41 in the second p-type well 39.

Referring to FIG. 11G, after removing the photoresist film 40, the photoresist film 42 is coated and patterned again to form an oxide film on the second p-well 39 adjacent to the channel stop region 41. 33) partially exposed. The VCCD channel region 43 is formed in the second p-type well 39 adjacent to the channel stop region 41 by ion implantation of n-type impurities into the second p-type well 39 through the exposed oxide layer 33.

The low concentration photodiode 35'-1 and the VCCD channel region 41 are separated by the high concentration p-type channel stop region 41 of the previous photodiode region 35 '. The VCCD channel region 43 has a higher impurity concentration than the second p-type well 39 and has a junction depth of 0.2 to 1.2 mu m.

Referring to FIG. 11 (11), a polysilicon film doped with an impurity is formed on the oxide film 33 and photo-etched to form the transfer gate electrode 44 only on the second p well 39.

P-type impurities are ion-implanted into the photodiode region 35 by self-aligning the transfer gate electrode 44 made of a polysilicon film doped with impurities with a mask to obtain a high concentration of p Form layer 45.

This p The layer 45 is formed under the surface of the photodiode region 35 with a junction depth of about 0.1 to 0.2 탆, and the impurity concentration is about 10 to 100 times higher than that of the photodiode region 35.

Therefore, the p-directional buried transfer gate channel region 39 'is formed between the VCCD channel region 43 and the photodiode region 35; The VCCD channel region 43 is count-doped on the second p well 39 and the second p well is formed due to the count doping by the side diffusion of the low concentration photodiode region 35-1 of the photodiode region 35. Lower impurity concentration than 39).

Referring to FIG. 11 (I), an oxide film is applied to the interlayer insulating film 46 on the entire substrate, and patterned so as to surround only the transfer gate electrode 44.

Subsequently, a metal, such as aluminum, is deposited on the entire surface of the substrate and patterned to form a light shielding film 47, and the oxide film 33 on the photodiode region 35 is exposed. An insulating interlayer 46 made of an oxide film is used to insulate the transfer gate electrode 44 from the light shielding film 47. The light shielding film 47 receives light in portions other than the photodiode region 35. It is to block things.

As described above, according to the present invention, the following effects can be obtained.

The photodiode region is formed deeper and wider in the structure of the conventional solid-state imaging device, thereby improving sensitivity to light in the red wavelength band, and reducing three-dimensional effects due to side diffusion, thereby improving anti-blooming characteristics.

In addition, since the VCCD channel region, which is a vertical transmission channel, exists in the cup-shaped second p well 39, the diffusion smear characteristic is improved, and the signal characteristic is moved to the bulk side when the transfer gate is turned on, thereby improving the noise characteristic.

In addition, the photodiode region is distributed in stages according to the position, and in the accumulation mode, most signal charges are accumulated in the high concentration photodiode closest to the VCCD channel region, so that the image-delay characteristics generated during reading are more than that of the conventional solid state imaging. There is an excellent advantage.

Claims (11)

The first conductive silicon substrate 31, the first well 32 of the second conductive type formed on the silicon substrate 31, and the plurality of wide and deep portions formed in the first well 32 at a predetermined interval from each other The first well type 32 overlaps the photodiode region 35 of the first conductivity type, the photodiode region 35, and the photodiode region 35 ′ adjacent to the photodiode region 35. A second well 39 of the second conductive type formed therein, a plurality of first conductive type VCCD channel regions 43 formed in the second well 39, a photodiode region 35 and a VCCD channel region ( The second conductive type transfer gate channel region 39 'formed in the second p well 39 between the second p well 39 and the VCCD channel region 43 and the previous photodiode region 35'. A channel stop region 41 of the second conductivity type formed in the second p well 39 for giving, a second impurity region 45 formed below the surface of each photodiode region 35, and a substrate front surface. The insulating film 33 of the thin film formed on the insulating film 33, the transfer gate electrode 44 formed on the insulating film 33 on the second well 39, and the interlayer formed on the insulating film 44 so as to audit the transfer gate electrode 44. And a light shielding film (47) formed on the entire surface of the substrate except for the insulating film (46) and the upper portion of each photodiode region (35). 2. The photodiode 35 of claim 1, wherein each photodiode region 35 has a relatively high concentration photodiode region 35-3, a medium concentration photodiode region 35-2, and a relatively low concentration photodiode region 35-1. And a stepwise concentration distribution in which the concentration increases toward the VCCD channel region 43. The CCD solid-state image pickup device according to claim 2, wherein each photodiode region (35) has a junction depth of about 1.5 to 3.5 mu m. The CCD solid-state image pickup device according to claim 1, wherein the second well (39) is a higher concentration impurity region than the n-type photodiode region (35). 5. The CCD solid state image pickup device according to claim 4, wherein the second well (39) has a fold depth of about 1.0 to 1.5 mu m. The CCD solid-state image pickup device according to claim 1, wherein the silicon substrate (31) of the first conductive type has a resistance value of about 10 to 100 占 Ωcm. The CCD solid-state image pickup device according to claim 1, wherein the first well (32) has a junction depth of about 3 to 6 mu m. A CCD solid-state image pickup device according to claim 1, wherein the transfer gate channel region (39 ') has a lower impurity concentration than the second well (39). The CCD solid-state image pickup device according to claim 1, wherein one of an oxide film and a nitride film is used as the insulating film (33). The impurity region 45 of the second conductive type has a junction depth of about 0.1 to 0.2 μm, and has a water purity concentration 10 to 100 times higher than that of the photodiode region 35. CCD solid-state imaging device. The CCD solid-state image pickup device according to claim 1, wherein the transfer gate electrode (44) is made of a polysilicon film doped with impurities.