KR940008252A - 2-phase non-overlapping clock generator - Google Patents

2-phase non-overlapping clock generator Download PDF

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Publication number
KR940008252A
KR940008252A KR1019920017428A KR920017428A KR940008252A KR 940008252 A KR940008252 A KR 940008252A KR 1019920017428 A KR1019920017428 A KR 1019920017428A KR 920017428 A KR920017428 A KR 920017428A KR 940008252 A KR940008252 A KR 940008252A
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KR
South Korea
Prior art keywords
phase
input
clock
clock generator
duty
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Application number
KR1019920017428A
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Korean (ko)
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KR950000351B1 (en
Inventor
강구창
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김주용
현대전자산업 주식회사
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Priority to KR1019920017428A priority Critical patent/KR950000351B1/en
Publication of KR940008252A publication Critical patent/KR940008252A/en
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Publication of KR950000351B1 publication Critical patent/KR950000351B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

입력클럭을 서로 중첩되지 않는 2가지 위상의 클럭으로 만들어 출력시키는 2위상 비중첩 클럭 발생기에, 입력클럭의 듀티에 제약을 받지 않고 고속의 비중첩 클럭을 발생시키기 위해 입력클럭의 한쪽 위상의 펄스폭을 늘이는 방향으로 동작하는 1차 듀티 조절기와, 입력클럭의 다른쪽 위상의 펄스폭을 늘이는 방향으로 동작하는 2차 듀티 조절기를 클럭발생기 앞단에 설치하여, 입력 클럭의 듀티에 무관하게 고속의 비중첩 클럭을 발생시킨다.In a two-phase non-overlapping clock generator that outputs the input clock as two phases of non-overlapping clocks, pulse width of one phase of the input clock to generate a high speed non-overlapping clock without being limited by the duty of the input clock. High speed non-overlapping by installing the primary duty controller which operates in the direction of increasing the and the second duty controller which operates in the direction of increasing the pulse width of the other phase of the input clock in front of the clock generator. Generate a clock.

Description

2위상 비중첩 클럭 발생기2-phase non-overlapping clock generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 2위상 비중첩 클럭 발생기 회로도.3 is a two phase non-overlapping clock generator circuit diagram in accordance with the present invention.

Claims (5)

입력클럭을 서로 중첩되지 않는 2가지 위상의 클럭으로 만들어 출력시키는 2위상 비중첩 클럭 발생기에 있어서, 입력 클럭의 한쪽 위상의 펄스폭을 늘이는 방향으로 동작하여 1단계로 입력클럭의 듀티(clock duty)를 조절하는 1차 듀티 조절기(10)와, 상기 1차 듀티 조절기(10)의 출력펄스를 입력받아 입력클럭의 다른쪽 위상의 펄스폭을 늘이는 방향으로 동작하여 2단계로 입력클럭의 듀티를 조절하는 2차 조절기(M1 내지 M5)를 포함하는 2위상 비중첩 클럭 발생기.In a two-phase, non-overlapping clock generator that outputs the input clocks by making clocks of two phases that do not overlap each other, the clock duty of the input clocks is operated in one step by increasing the pulse width of one phase of the input clock. The duty cycle of the input clock is adjusted in two stages by operating in a direction of increasing the pulse width of the other phase of the input clock by receiving the primary duty controller 10 and the output pulse of the primary duty controller 10. Two-phase non-overlapping clock generator comprising a secondary regulator (M1 to M5). 제1항에 있어서, 상기 2차 듀티 조절기는 클럭 발생기로 입력되는 내부 클럭 ICK의 한쪽 위상의 펄스가 완전히 전달된후, 다른쪽 위상의 펄스가 전달될 수 있도록 피드백신호를 피드백신호를 보내주는 소자(M5)를 포함하는 2위상 비중첩 클럭 발생기.The device of claim 1, wherein the secondary duty controller sends a feedback signal to the feedback signal so that a pulse of one phase of the internal clock ICK, which is input to the clock generator, is completely delivered, and then a pulse of the other phase is transmitted. A two phase non-overlapping clock generator comprising M5. 제2항에 있어서, 상기 2차 듀티 조절기는 입력에 의해 온, 오프되면 각각 Vcc노드 및 접지 노드에 연결되어 있는 소자 M1 및 M3와, 상기 소자 M1 및 M3사이에 연결되며 상기 피드백신호에 의해 온, 오프되는 소자 M2를 포함하는 2위상 비중첩 클럭 발생기.3. The secondary duty regulator of claim 2, wherein the secondary duty controller is connected between the elements M1 and M3 connected to the Vcc node and the ground node, respectively, when the secondary duty regulator is turned on and off by an input, and is turned on by the feedback signal. , A two-phase non-overlapping clock generator comprising the device M2 is turned off. 제2항에 또는 제3항에 있어서, 상기 피드백신호에 의해 온, 오프되는 소자 M2는 입력에 의해 조정되며 접지노드에 연결되는 소자 M3보다 내부 클럭 ICK 노드쪽에 가까이 배치되는 2위상 비중첩 클럭 발생기.4. The two-phase non-overlapping clock generator according to claim 2 or 3, wherein the element M2 turned on and off by the feedback signal is adjusted by an input and disposed closer to the internal clock ICK node than the element M3 connected to the ground node. . 제1항에 있어서, 상기 1차 듀티 조절기를 TTL호환성 클럭 버퍼로 대체한 2위상 비중첩 클럭 발생기.2. The two phase, non-overlapping clock generator of claim 1 wherein the primary duty controller is replaced with a TTL compatible clock buffer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920017428A 1992-09-24 1992-09-24 Two phase non-overlap clock generator KR950000351B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920017428A KR950000351B1 (en) 1992-09-24 1992-09-24 Two phase non-overlap clock generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920017428A KR950000351B1 (en) 1992-09-24 1992-09-24 Two phase non-overlap clock generator

Publications (2)

Publication Number Publication Date
KR940008252A true KR940008252A (en) 1994-04-29
KR950000351B1 KR950000351B1 (en) 1995-01-13

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KR1019920017428A KR950000351B1 (en) 1992-09-24 1992-09-24 Two phase non-overlap clock generator

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KR950000351B1 (en) 1995-01-13

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