KR940007462B1 - Pseudo soi semiconductor device and method of making the same - Google Patents

Abstract

The device comprises a seed substrate (1), the first sub electrode layer and the second sub electrode layer (8a,8b) which are divided by a isolating layer, an isolating layer (6a) which is shaped by LOCOS (local oxidation of silicon) and separated as element units, a silicon layer where a source (15a) and a drain (15b) are located, an active region of epitaxial layer (1a) which has a thiner single stepped structure than the silicon layer and, a sub-contact of channel which is in contact with the first sub-electrode layer and the second sublayer (8a,8b) and is inputted by sub-potential from an electrode layer.

Description

Pseudo SOI semiconductor device and manufacturing method thereof

1 is a cross-sectional view illustrating the structure of a conventional SOI semiconductor device.

2 is a cross-sectional view schematically illustrating the structure of main parts of a pseudo SOI semiconductor device to which the present invention is applied.

3A to 1B illustrate a manufacturing process of a pseudo SOI semiconductor device according to one embodiment of the present invention.

4 is a diagram illustrating a structure in which sub-contacts and sub-electrodes are formed in a manufacturing process of a pseudo SOI semiconductor device according to a second embodiment of the present invention.

5A and 5B illustrate structures in which sub-contacts and sub-electrodes are formed in a manufacturing process of a pseudo SOI semiconductor device according to a third embodiment of the present invention.

6A to 6C illustrate a step of forming a step on a surface of a seed substrate in a manufacturing process of a pseudo SOI semiconductor device according to a fourth embodiment of the present invention.

7 is a sectional view of a pseudo SOI semiconductor device manufactured by a manufacturing process according to the present invention.

8 is a plan view of FIG.

9 is an equivalent circuit diagram of the pseudo SOI semiconductor device shown in FIG.

* Explanation of symbols for main parts of the drawings

1: seed substrate 1C: support substrate

2, 6: silicon oxide film 8: electrode layer

7, 16: insulating film 11a, 11b: active region

13 gate electrode 15 gate oxide film

15a, 15b: source / drain

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a pseudo-SOI semiconductor device and a method of manufacturing the same, and more particularly, to a pseudo SOI CMOS inverter having a partially different thickness of a silicon thin film layer in an active region in which a CMOS device is formed. It relates to a manufacturing method.

In the conventional SOI (Silicon on Isulator) MOS device, since the active region is formed on the insulating film formed on the substrate without a step, floating phenomenon occurs in the channel region.

A schematic structure of such a conventional SOI MOS device is shown in FIG.

In Fig. 1, 1c is a semiconductor substrate, 2 is an insulating film formed over the entire surface of the semiconductor substrate 1, 6 is an insulating film for element isolation, 11 is a channel region of the MOS element formed in the active region, and 15b is a source and a drain region, respectively.

In the above structure, since the entire active region is entirely isolated from the substrate 1 by the insulating film 2 formed on the substrate 1, the channel region 11 of the MOS element formed in this active region is Electrically floating.

This floating phenomenon becomes a factor of lowering the electrical characteristics of the MOS device.

The SOI MOS device is an element having an advantage of easy device isolation by an insulating layer and minimizing the junction parasitic capacitance of the source / drain, but the device characteristics are deteriorated due to the floating phenomenon of the channel region as described above.

In order to solve this problem, Korean Patent Application No. 91-18984 filed by the same applicant can prevent the occurrence of the above floating phenomenon, and furthermore, a pseudo SOI semiconductor having a structure which further improves the minimization of the junction parasitic capacity. A technique relating to a device and a method for manufacturing a semiconductor device for manufacturing such a structure is disclosed.

The present invention relates to a technique applied to a pseudo SOI CMOS inverter by improving the technique of Patent Application No. 91-18984. Accordingly, the first object of the present invention is to improve the operation characteristics of the device by preventing the occurrence of channel floating while maintaining the ease of device isolation and minimizing the source / drain junction capacitance of the conventional SOI semiconductor device. The present invention provides a pseudo SOI CMOS inverter and a method of manufacturing the same.

A second object of the present invention is to facilitate the layout of the electrode wiring in the upper layer by embedding a portion of the electrode wiring in the lower layer, thereby facilitating the layout (lay-out), such as device arrangement and wiring arrangement in the chip design The present invention provides a pseudo SOI CMOS inverter and a method of manufacturing the same.

It is a third object of the present invention to provide a pseudo SOI CMOS inverter and a method of manufacturing the same, which can be performed by separating the upper and lower layers in a semiconductor manufacturing process, thereby ensuring a large margin of each manufacturing process.

A fourth object of the present invention is to provide a pseudo SOI CMOS inverter capable of simplifying a manufacturing process by simultaneously performing a well formed in a channel region in a process of forming a second sub-contact and a second sub-electrode, without performing a separate process. It is to provide a manufacturing method.

The fifth object of the present invention is to form a silicon oxide film in the case of forming the first and second sub-contacts and sub-electrodes, and then to cover the sub-contacts in addition to the step of forming the sub-contacts and sub-electrodes. Pseudo SOI CMOS which reduces the misalignment that can occur in sub-contact formation because it uses the process of forming the second electrode or the process of forming the sub-contact and the sub-electrode using photoresist coating. The present invention provides an inverter and a method of manufacturing the same.

A sixth object of the present invention is to provide a pseudo SOI CMOS inverter and a method of manufacturing the same, which can reduce the number of steps using a step of directly forming a step on the surface of the seed substrate.

According to a feature of the present invention, the pseudo SOI CMOS inverter partially changes the thickness of the silicon thin film layer in the active region in which the CMOS element is formed so that the source and drain of the silicon thin film layer at the position where the channel of the MOS device is formed are formed. The silicon thin film layer is formed to be relatively thicker than the thickness of the silicon thin film layer at the position where the silicon thin film layer is formed, and the silicon thin film layer at the position where the source and drain are formed is formed on the insulating film, and the silicon thin film layer at the channel position is formed of the first and second sub-contacts. And direct contact with the first and second electrode layers such that a sub-potential is applied through.

According to a manufacturing method for manufacturing the pseudo SOI CMOS inverter, the plurality of substrates may include a plurality of substrates including a seed substrate on which an active element is formed and a handle substrate for maintaining support strength. A pretreatment step of forming an active region, a sub contact, and a sub-electrode of the semiconductor device on the seed substrate before bonding the substrate, a bonding step of bonding the formed semiconductor substrate, and a post-treatment step performed after the bonding step. In the method of manufacturing a semiconductor device, the pretreatment step includes forming a well in the epitaxial layer 1b of the seed substrate 1 and a silicon oxide film 2b on the seed substrate 1 on which the well is formed. And sequentially stacking the silicon nitride film 4a and the silicon oxide film 5, and then defining the channel region with the photoresist 3b, and the image according to the channel region defined by the process. Etching the oxide films 2b, 4a, and 5 formed on the seed substrate 1, followed by etching the epitaxial layer 1b of the seed substrate 1 to a predetermined depth; and epitaxial etched by the process Forming a field oxide film 6a on the seed substrate 1 having the shir layer 1b, which is used as a layer for preventing electrical isolation and polishing between elements, and electrically insulating the source / drain and electrode layers of the device. For this purpose, the silicon oxide film 6b is grown to a predetermined thickness between the field oxide films 6a, and the silicon nitride film 4a and silicon oxide film 2b formed in the channel region defining process are removed. And depositing polycrystalline silicon, and then injecting a P-type or N-type dopant to form a first sub-electrode 8a by depositing 7a), and forming the first sub-contact 9a. The silicon oxide film 7b is placed on the substrate on which the sub-electrodes 8a are formed. After deposition, a second sub-contact 9b is formed, followed by deposition of polycrystalline silicon, followed by injection of a P-type or N-type dopant to form a second sub-electrode 8b, on which the silicon oxide film 7c and the polycrystal are deposited. And a step of forming silicon 10 sequentially, wherein the substrate bonding step includes surface contact between the polycrystalline silicon 10 of the seed substrate 1 and the silicon insulating film 2d formed on the support substrate 1c. Bonding the seed substrate 1 to the support substrate 1C by heat treatment; wet etching the single crystal silicon layer 1a of the seed substrate 1 to leave only the epitaxial layer 1b; Polishing the epitaxial layer 1b to the interface of the field oxide film 6a so that only the active regions 11a and 11b remain, and the post-treatment process includes the active region 11a of the epitaxial layer 1b. Gate oxide film 12 is formed on the gate oxide film 12b. Forming a pole 13 and then forming a side waoo 14 on the sidewall of the gate layer; and a silicon oxide film on the entire surface of the epitaxial layer 1b including the gate electrode 13. 16) and then forming contact (17a, 17b) of the source / drain regions by photoresist, and subsequently forming metal thin films (18a-18c). to be.

According to another aspect of the present invention, a method of manufacturing a pseudo SOI CMOS inverter is a method of forming a second sub-contact and a second sub-electrode in the process of forming the second sub-contact and the second sub-electrode without performing the well process separately. And spreading the doped N-type and P-type dopants to the epitaxial layer of the seed substrate through each subcontact.

According to still another aspect of the present invention, in the method of manufacturing a pseudo SOI CMOS inverter, the first and second sub-contact covers are formed on the first and second sub-contacts in the first and second sub-electrode forming steps. Forming a second sub-electrode.

According to another aspect of the present invention, a method of manufacturing a pseudo SOI CMOS inverter includes a step of forming first and second sub-electrodes by using a photosensitive film in the first and second sub-electrode formation steps.

According to still another aspect of the present invention, a method of manufacturing a pseudo SOI CMOS inverter includes a step of forming a step at a position corresponding to an active region of a device on a surface of a seed substrate.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 shows a schematic structure of an SOI MOS device according to the present invention.

In FIG. 2, a pseudo SOI MOS device is fabricated by joining two substrates along the AA 'interface. In this figure, the structural characteristics of the pseudo SOI MOS device which can be distinguished from the conventional SOI MOS device shown in FIG. The source 15a and the drain 15b of the Morse element are separated from each other by the insulating film 6a formed by LOCOS and used as the active regions 11a and 11b which are the positions where the Morse element is formed. The formed portion is relatively thinner than the portion in which the channel 11b is formed in the silicon thin film layer, and the forming portions of the source 15a and the drain 15b are formed by the insulating layer 6b and the electrode layer 10a. The parts which are electrically isolated and the channel 11b are formed are electrically connected to the electrode layer 10a through sub-contacts so that subpotentials can be applied.

The pseudo SOI MOS device having such a structure is suspended because the subpotential is applied through the subcontact of the channel in the channel while maintaining the ease of device isolation and minimization of the junction capacitance, which are advantages of the conventional SOI MOS device. It is possible to prevent the occurrence of the phenomenon and to further improve the minimization of the junction parasitic capacity.

In the drawing, reference numerals 1c and 2d are respectively a support wafer (handel wafer) located at the lower end of the interface AA 'and a silicon insulating film coated on the support substrate 1c, and 13 and 12 denote the active regions 11a and 11b. A gate electrode and a gate insulating film sequentially stacked on top.

In addition, a structure formed at an upper portion along the interface AA ′ is formed on a seed wafer.

The manufacturing process of such a pseudo SOI MOS device of the present invention will be described with reference to FIGS.

This manufacturing process is largely a pretreatment step of forming an element isolation oxide film, an active region and an electrode of a SOI MOS device on a seed substrate, and a substrate bonding which bonds the CD substrate and the supporting substrate coated with an insulating film and thins the seed substrate. And a post-treatment step of forming an electrode in a state where the two substrates are bonded to each other.

In FIG. 3, the drawings a to g show the pretreatment process, the drawings h to j show the bonding process, and the drawings k to l show the post treatment process.

First, the pretreatment steps a to g will be described.

As shown in FIG. 3A, the well-forming process, which is the first process, forms a silicon oxide film 2a on the top surface of the seed substrate 1 and then includes a well in a portion where a channel is formed by the photoresist 3a. ) And a p-type or n-type dopant is implanted into the epitaxial layer 1b of the seed substrate 1 through the location of the well.

The material of the dopant is determined according to the properties of the epitaxial layer of the seed substrate.

Then, the photoresist 3a formed on the silicon oxide film 2a is removed, and then the depth of the well is adjusted by a heat treatment process. At this time, the depth of the well should be thinner than the thickness of the epitaxial layer 1b of the seed substrate.

As the epitaxial layer 1b is grown on the original plate 1a of the seed substrate 1, when the P ⁺ disc is used, the P ^_ epitaxial layer is grown, and when the N ⁺ disc is used, the N-epitaxial layer is Is formed.

Meanwhile, if necessary, twin wells may be formed using the well forming process.

In the process of defining the channel region as the second process, the silicon oxide film 2b, the silicon nitride film 4a, and the silicon oxide film 5 are again placed on the seed substrate 1 on which the well is formed, as shown in FIG. After sequentially stacking, the channel region is defined as a photoresist 3b.

In the epitaxial layer etching process as a third process, as shown in FIG. 3C, the insulating films 2b, 4a, and 5 are sequentially etched by RIE according to the channel region defined by the second process. Subsequently, the epitaxial layer 1b of the seed substrate 1 is etched to a predetermined depth.

In this case, the etch depth of the epitaxial layer of the seed substrate is determined in consideration of the difference between the single crystal silicon thickness of the channel region of the device and the single crystal silicon thickness of the source / drain regions.

The epitaxial layer etching process of the seed substrate as the fourth process is performed again on the entire surface of the seed substrate 1 having the epitaxial layer 1b etched by the third process, as shown in FIG. After the silicon oxide film 2c and the silicon nitride film 4b are formed, the field oxide film 6a is formed by local oxidation of silicon (LOCOS) growth while defining an active region.

The field oxide film 6a thus formed is used as a stopper for polishing for the electrical isolation between the elements and the thinning of the seed substrate 1.

The silicon oxide film forming process as the fifth process is performed by the silicon oxide film 2c, silicon nitride film 4b, and silicon oxide film formed on the seed substrate 1 in the fourth process as shown in FIG. After removing (5) by known wet etching, the silicon oxide film 6b is grown again.

At this time, the formed silicon oxide film 6b has a function to electrically insulate the source / drain of the device from the electrode layer formed later, and is formed thinner than the thickness of the field oxide film 6a formed in the fourth process.

In addition, the thickness of the single crystal silicon of the source / drain regions of the pseudo SOI semiconductor device finally formed is determined according to the difference between the thicknesses of the silicon oxide film 6b and the field oxide film 6a.

In the sixth step of forming the first sub-contact and the first sub-electrode, the silicon nitride film 4a and the silicon oxide film 2b formed in the second process are removed by wet etching as shown in FIG. The oxide film 7a is deposited to form the first sub contact 9a. Subsequently, polycrystalline silicon is deposited to inject a P-type or N-type dopant to form the first sub-electrode 8a.

In the seventh step, the second sub-contact and the second sub-electrode formation step are performed by the silicon oxide film 7b on the supporting substrate including the first sub-electrode 8a formed by the sixth step, as shown in FIG. ) And then the second sub-contact 9b is formed, and then polycrystalline silicon is deposited to inject the P-type or N-type dopant to form the second sub-electrode 8b.

In addition, the silicon oxide film 7c and the polycrystalline silicon layer 10 are sequentially formed thereon, and then the surface of the polycrystalline silicon layer 10 is smoothly polished.

Next, a substrate bonding process h to j is formed to bond the seed substrate and the support substrate and to thin the seed substrate.

In the substrate bonding step of the eighth step, as shown in FIG. 3H, the silicon insulating film 2d and the seed substrate 1 are polished with the silicon insulating film 2d formed on the support substrate 1c. The polycrystalline silicon layer 10 is brought into surface contact and then heat treated to bond the seed substrate and the support substrate.

In the ninth step, the step of etching the single crystal silicon 1a of the seed substrate 1 is made of hydrofluoric acid (HF), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH), as shown in FIG. The etch solution is used to etch away the single crystal silicon 1a of the seed substrate 1 bonded to the support substrate 1C.

As a result, only the epitaxial layer 1b remains on the seed substrate 1.

In the epitaxial layer polishing step, which is a tenth step, the epitaxial layer 1b remaining by the eighth step is polished as shown in FIG.

At this time, the thickness of the silicon single crystals, which are the active regions 11a and 11b of the epitaxial layer 1b, which is finally left, is determined by the thickness of the silicon oxide film that is settled inside when the field oxide film 6a is formed by the fourth process. do.

This is because polishing is inhibited at the interface of the field oxide film 6a during polishing.

Thus, the seed substrate 1 is finally thinned, leaving only the active regions 11a and 11b.

At this time, if necessary, the well forming process is performed again in the active region.

Next, the post-processing steps k to l which are electrode forming steps will be described.

The gate electrode forming process, which is the eleventh process, forms a gate oxide film 12 in the active regions 11a and 11b of the epitaxial layer 1b and then on the gate oxide film 12, as shown in FIG. Polycrystalline silicon, polyside or refractory metal forms the gate electrode 13.

Subsequently, a sidewall 14 is formed on the gate layer, and then the source / drain is separated using a photoresist.

In the twelfth step of the source drain contact forming process, as shown in FIG. 3, the silicon oxide film 16 is formed on the entire surface of the epitaxial layer 1b including the gate electrode 13 formed by the eleventh process. Is deposited and then the contacts of the source / drain regions 17a and 17b are formed using a photoresist.

The metal thin films 18a to 18c are deposited on the contact to complete the pattern of the source / drain electrodes.

Meanwhile, the well forming process as the first process in the first embodiment may be omitted, and the wells may be formed in the first and second sub-electrode forming processes as the sixth and seventh processes.

That is, in FIG. 3G, the N-type and P-type dopants doped to the first sub-electrode 8a and the first sub-electrode 8b, which are the electrodes for subpotential application, respectively, are used for the first and second subs. It can be diffused directly into the epitaxial layer 1b through the contacts 9a and 9b to form a retrograded twin-well.

As described above, the process number is reduced by automatically forming the wells when impurities are injected into the polycrystalline silicon layers for the electrodes 8a and 8b without performing a separate well forming process as in the first embodiment. Can be.

The following describes a second embodiment of the present invention with reference to FIG.

The silicon nitride film 4a and the silicon oxide film 2b remaining in the silicon oxide film forming process (see FIG. 3E) as the fifth process are removed by wet etching.

Subsequently, prior to the sixth and seventh processes of forming the sub-contact and the sub-electrode, the sub-contact covers 8aa and 8bb are deposited by depositing a polycrystalline silicon or silicide electrode layer on the self-aligned sub-contacts 9a and 9b. After the formation, the sixth and seventh processes are performed.

That is, after the sub contact covers 8aa and 8bb are formed, the silicon oxide film 7a is deposited to form a sub contact 9bb, and then polycrystalline silicon or silicide, which is an electrode layer for the first sub-electrode, is deposited thereon. After that, a pattern is formed to form the first sub-electrode 8b.

Subsequently, the silicon oxide film 7b is further deposited, and then a sub contact 9aa is formed, and a second sub-electrode 8a is formed by double depositing polycrystalline silicon on the polycrystalline silicon or silicide as an electrode layer for the second sub-electrode thereon. do.

Next, a third embodiment according to the present invention will be described with reference to Figs.

This embodiment relates to the process of forming the first and second sub-contacts and sub-electrodes as in the second embodiment.

After the fifth process in the first embodiment is performed, a pattern is defined by applying a photosensitive film 19 onto a seed substrate including the remaining silicon nitride film 4a and silicon oxide film 2b.

At this time, the silicon nitride film 4a and the silicon oxide film 2b are selectively removed by the pattern (see FIG. 5A).

After forming the self-aligned first sub-contact 20a, the remaining photoresist film 19 is removed, and polycrystalline silicon or silicide is deposited to form a pattern thereon to form the first sub-electrode 21a thereon. .

Subsequently, the silicon oxide film 20 is deposited, and then a pattern is defined.

Then, the silicon nitride film 4a and the silicon nitride film 4b are removed to form a self-aligned second sub contact 20b, and polycrystalline silicon or silicide and polycrystalline silicon are sequentially deposited thereon to form the second sub-electrode 21b. Form.

As a result, alignment errors may be reduced in forming the sub-contact.

A fourth embodiment according to the present invention will be described with reference to Figs. 6A to 6C.

This embodiment is a method of forming a step directly on the surface of the seed substrate in manufacturing an SOI substrate having silicon thin film layers of different thicknesses.

In FIG. 6A, the silicon oxide film 26 and the silicon nitride film 4a are first formed on the seed substrate 1, the device active region is defined, and the silicon oxide film 6a is thermally grown by a general LOCOS method.

In FIG. 6B, the first step 5 is formed by removing the silicon oxide film 6a formed by the above method, the channel region is defined through exposure, and then the silicon nitride film outside the channel region using the photoresist 3a. (4a) The silicon oxide film 2b was shown to be removed by dry etching.

In FIG. 6C, the photoresist 3a is first removed, and then the second step is formed by dry etching the epitaxial layer of the seed substrate using the silicon nitride film 4a remaining in the channel region as a mask layer. After that, the silicon oxide film 6b is thermally grown.

The seed substrate on which this process is performed has a double step on the surface, and thus has a conceptually identical structure to the sidigg pin shown in FIG.

As such, by forming a step directly on the seed substrate, the overall manufacturing process of the pseudo SOI CMOS inverter can be reduced.

The pseudo SOI MOS device completed by the above manufacturing method coincides with that shown in FIG.

Referring to the pseudo SOI CMOS element structure of FIG. 7, channels of NMOS and PMOS are formed in (11a) and (11b), and sources and drains are formed in (15a) and (15b), respectively.

The gate is formed at 13, and electrical isolation between the elements is made by the first insulating film 6a.

In particular, the source and drain of the NMOS and PMOS are electrically isolated from the lower layer by the second insulating film 6b, while the channel regions 11a and 11b are subpotentials through the subcontacts 9a and 9b. It is electrically connected with the application electrode layers 8a and 8b.

In addition, (7a) and (7b) are the third and fourth insulating film for forming the sub-contact, (2d) is a fifth insulating film for bonding the seed substrate and the support substrate.

And 18a, 18b, and 18c are connection wirings for electrical connection.

8 is a plan view of a pseudo SOI CMOS inverter having such a structure.

In FIG. 8, reference numeral 100 denotes a portion where a well of a pseudo SOI CMOS logic gate is to be formed, and 102a and 102b denote a portion where a gate of NMOS and PMOS is to be formed. This corresponds to part (11b).

103a and 103b define an active define region, and 104a and 104b are subcontacts for connection with an electrode layer for applying subpotentials to channel regions of NMOS and PMOS.

The subpotential application electrode layers are separately formed as necessary for the NMOS and the PMOS, respectively. Here, the cases are formed separately.

The electrode layer for subpotential application connected to the subcontacts 104a and 104b does not appear on the plan view of FIG. 8.

Referring to FIG. 7, the subcontacts 104a and 104b of FIG. 8 correspond to 9a and b of FIG. 7, and the electrode layer for applying subpotentials connected to the subcontact 104a of FIG. An electrode layer corresponding to (8a) of FIG. 8 and a subpotential application electrode layer connected to another sub contact 104b of FIG. 8 correspond to (8b) of FIG.

In FIG. 8, 105a and 105b define the gates of the NMOS and PMOS, 106a, 106a ', 106a ", 106b, 106b', 106b" define the contact of the source drain and gate, Reference numerals 107a, 107b 107c, and 107d define interconnections for connection between the devices.

FIG. 9 shows an electrical equivalent circuit of the logic gate inverter shown in FIGS. 8 and 7, and the numbers of FIG.

As described above, according to the present invention, the pseudo SOI semiconductor device can apply a voltage through the sub-contact to solve the shortcomings of the device operation characteristics due to the channel floating phenomenon, and because the source / drain region is placed on the insulating film Parasitic doses can be minimized.

In addition, the isolation between the devices can be minimized by mutually isolating neighboring devices using an insulating film.

In addition, it is possible to greatly increase the margin in each process by dividing the process of the upper part and the lower part, and in particular, it is easy to arrange the electrode wiring in the upper part by embedding a part of the electrode wiring in the lower layer. In design, layout such as device layout and wiring layout can be easily performed.

Claims (24)

In an SOI semiconductor device formed by joining a support substrate coated with an insulating film, an epitaxial layer 1b, and a seed substrate on which an active region of an SOI CMOS element is formed, wherein the electrode is formed on the insulating film, and each electrode is formed on the insulating film. The first and second sub-electrode layers 8a and 8b electrically separated by the insulating layer 6a and the insulating layer 6a formed by LOCOS, and are separated by element, and the source 15a and the drain 1bb are positioned. The active layer of the epitaxial layer 1b having a stepped structure that is relatively thinner than the thickness of the silicon layer at the position where the channels 11a and 11b are formed, and the source 15a and the drain 15b of the active region ) And an insulating film which electrically insulates only the first sub-electrode layer and the first sub-electrode layers 8a and 8b, and the channel of the active region is in contact with the sub-electrode layers 8a and 8b so that the subpotential is formed from the electrode layer. Loin And a sub-contact of said channel to be applied. The pseudo SOI semiconductor device according to claim 1, wherein the thicknesses of the source (15a) and the drain (15b) are determined by the thickness of the insulating film formed on the epitaxial layer (1b) of the seed substrate (1). . A pretreatment step of forming an active region of an SOI MOS device, an oxide layer for separating a device, and a sub-electrode on a seed substrate having a plurality of substrates on which an epitaxial layer is formed; and bonding the seed substrate and the support substrate coated with an insulating film. A method of manufacturing an SOI semiconductor device comprising a substrate bonding step of thinning a seed substrate and a post-treatment step of forming an electrode in a state in which the two substrates are joined, wherein the pretreatment step includes an epitaxial layer of the seed substrate 1. A step of forming a well in 1b), a silicon oxide film 2b, a silicon nitride film 4a, and a silicon oxide film 5 sequentially stacked on the seed substrate 1 on which the well is formed, and then a channel with a photoresist 3b. A step of defining a region, a step of forming a step in the epitaxial layer of the seed substrate according to the difference between the channel region depth and the source / drain region depth of the device, and the channel region defining process The formed silicon nitride film 4a and the silicon oxide film 2b are removed, the silicon oxide film 7a is deposited, and the first and second sub-contacts 9a and 9b and the first and second sub-electrodes 8a, 8b), and sequentially forming a silicon oxide film 7c and a polycrystalline silicon layer 10 thereon, wherein the substrate bonding process includes the polycrystalline silicon 10 and the supporting substrate (1) of the seed substrate 1; Bonding the seed substrate 1 to the support substrate 1c by surface-contacting the silicon insulating film 2d formed on 1c and then heat-treating, and wetting the single crystal silicon layer 1a of the seed substrate 1 Etching to leave only the epitaxial layer 1b, and polishing the epitaxial layer 1b to the interface of the field oxide film 6a so that only active regions 11a and 11b remain. The treatment step forms a gate oxide film 12 in the active region of the epitaxial layers 11a and 11b, and the gate oxide Forming a gate electrode 13 on (12), and then forming sidewalls 14 on the side of the gate layer, and silicon on the entire surface of the epitaxial layer 1b including the gate electrode 13. And depositing the oxide film 16, and then forming the contacts 17a and 17b of the source / drain regions by photoresist, and then forming the metal thin films 18a to 18c. Manufacturing method. 4. The well forming process according to claim 3, wherein the well forming process is performed by applying a silicon oxide film (2a) to the entire surface of the seed substrate (1), and then defining a well with a photoresist (3a), And implanting an N-type or P-type dopant in accordance with the properties of the epitaxial layer. The method of manufacturing a pseudo SOI semiconductor device according to claim 3 or 4, wherein the well forming step determines the depth of the well by injecting the dopant and then performing a heat treatment step. The method of manufacturing a pseudo SOI semiconductor device according to claim 3 or 4, wherein a double well is formed on an epitaxial layer (1b) of said seed substrate (1) using said well forming process. 4. The step forming process according to claim 3, wherein the step forming step etches away the oxide films (2b, 4a, 5) formed on the seed substrate (1) according to the channel region defined by the process. A field used for etching the tactile layer 1b to a predetermined depth, and as a layer for preventing electrical isolation and polishing between elements on the seed substrate 1 having the epitaxial layer 1b etched by the above process. Forming an oxide film 6a, and growing a silicon oxide film 6b to a predetermined thickness between the field oxide films 6a to electrically insulate the source / drain and electrode layers of the device. A method of manufacturing a pseudo SOI semiconductor device. 4. The method of claim 3, wherein the step of forming a step on the seed substrate defines an active region of a next device for forming a silicon oxide film 2b and a silicon nitride film 4a on the seed substrate 1, thereby forming a silicon oxide film for device isolation. (6a) and then removing the silicon oxide film (6a) to form a first step, defining a channel region through an exposure operation, and then using a photoresist (3a) and a silicon nitride film outside the channel region. Removing the silicon oxide film, and removing the photoresist on the remaining silicon nitride film, and then etching the epitaxial layer 1b of the seed substrate using the silicon nitride film as a mask layer to form a second step. 6b) forming a pseudo SOI semiconductor device. 8. The field oxide film forming process according to claim 7, wherein the field oxide film forming process forms a silicon oxide film 2c and a silicon nitride film 4b on the entire surface of the etched seed substrate 1, and then defines an active element to form the field oxide film 6a. A method of manufacturing a pseudo SOI semiconductor device. The method of manufacturing a pseudo SOI semiconductor device according to any one of claims 7 to 9, wherein the field oxide film forming step is performed by LOCOS growth. 4. The process of claim 3, wherein the silicon oxide film 6b growth process includes the silicon oxide film 2c, the silicon nitride film 4b, and the silicon oxide film 5 formed in the channel region defining process applied in the field oxide film forming process. And then forming a silicon oxide film (6b) to a predetermined thickness again. The method of manufacturing a pseudo SOI semiconductor device according to claim 3 or 11, wherein the silicon oxide film (6b) formed in the silicon oxide film growth step is formed to have a thickness relatively thinner than that of the field oxide film (6a). 12. The thickness of the single crystal silicon of the source / drain regions of the device is determined according to the thickness difference between the silicon oxide film 6b and the field oxide film 6a formed in the silicon oxide film growth process. A method of manufacturing a pseudo SOI semiconductor device. 4. The method according to claim 3, wherein the insulating film (2c, 4b, 5) is removed by a wet etching process in the silicon oxide film growth process. 4. The method of claim 3, wherein the first and second sub-contacts and sub-electrodes form a first sub-contact 9a, and then polycrystalline silicon is deposited on the entire surface, followed by injection of a P-type or N-type dopant. Forming a first sub-electrode 8a, depositing a silicon oxide film 7b on the substrate on which the first sub-electrode 8a is formed, forming a second sub-contact 9b, and then depositing polycrystalline silicon And then implanting a P-type or N-type dopant to form a second sub-electrode (8b). 16. The pseudo SOI semiconductor device according to claim 3 or 15, wherein the second sub-electrode forming step includes the step of polishing the surface of the polycrystalline silicon layer after the polycrystalline silicon layer 10 is formed. Manufacturing method. 4. The method of claim 3, wherein the thin film is completed in the single crystal silicon etching process of the seed substrate and then a well forming process is added. 4. A method according to claim 3, wherein the gate electrode (13) is formed of polycrystalline silicon, polyside or refractory metal in the gate electrode forming step. 19. The method of manufacturing a pseudo SOI semiconductor device according to claim 18, further comprising forming a gate electrode (13) and then forming a side wall (14) by said gate electrode forming step. 4. The method of claim 3, wherein a dopant is implanted through the sub-contacts (9a, 9b) to form a well in the epitaxial layer (1b). 4. The method of claim 3, wherein the sub-electrode forming process removes the silicon nitride film 4a and the silicon oxide film 2b formed in the channel region defining process to remove the first step sub-contacts 9a and 9b of the channel region. Form a sub-contact cover 8aa, 8bb by depositing an electrode layer thereon, and then deposit a silicon oxide film 7a, and then form a second step sub-contact 9bb on the sub-contact cover 8bb. And forming a first sub-electrode 8b on the second sub-contact 9bb, and then depositing a silicon oxide film 7b, followed by a third-stage sub-contact on the sub-contact cover 8aa. 9aa), and a second subelectrode 8a, which is a double electrode layer, is formed on the third step subcontact 9aa, and the silicon oxide film 7c and the polycrystalline silicon layer 10 are sequentially formed thereon. A method of manufacturing a pseudo SOI semiconductor device, comprising the step of; 22. The pseudo SOI semiconductor device according to claim 21, wherein the electrode layers of the sub contact covers 8aa and 8bb are formed of polycrystalline silicon, polysides, or refractory metals in the second step of forming the subcontacts 9bb. Manufacturing method. 22. The method of claim 21, wherein in the second sub-electrode forming step, the double electrode layer is formed of polycrystalline silicon, polyside, or refractory metal. The method of claim 3, wherein the sub-electrode forming plant defines a pattern by applying a photosensitive film 19 on the seed substrate 1 on which the silicon nitride film 4a and the silicon oxide film 2b formed in the channel region defining process are formed. Selectively removing the silicon nitride film 4a and the silicon oxide film 2b to form a first sub contact 20a, removing the remaining photoresist film 19, and then removing the silicon nitride film 4a and the silicon oxide film 2b on the first sub contact 20a. Forming a first sub-electrode 21a on the first sub-electrode 21a, depositing a silicon oxide film 22 thereon, and defining a pattern for the second sub-contact, and remaining silicon nitride film 4a. And removing the silicon oxide film (4b) to form a second sub-contact (20b) and then forming a second sub-electrode (21b) as a double electrode layer.