KR940002693A

KR940002693A - Data reproduction circuit in DAT system

Info

Publication number: KR940002693A
Application number: KR1019920012734A
Authority: KR
Inventors: 박판기
Original assignee: 강진구; 삼성전자주식회사
Priority date: 1992-07-16
Filing date: 1992-07-16
Publication date: 1994-02-19
Also published as: KR0171907B1

Abstract

DAT시스템의 데이터 재생회로에 있어, 순수 DAT에 필요한 데이터만을 보관하기 위한 메모리부와, 시스템콘트롤러인 마이콤과, 상기 마이콤으로 부터 발생된 어드레스 데이터를 받아 기본 어드레스 값으로 저장기에 저정한다.In the data reproducing circuit of the DAT system, a memory unit for storing only data necessary for pure DAT, a microcomputer as a system controller, and address data generated from the microcomputer are received and stored in the storage unit as a basic address value.

DAT테이프에서 출력되는 직렬 데이터단의 입력을 비트클럭단의 신호에 의해 고속신호 처리를 위해 병렬 데이터로 변환하고, 상기 비트클럭단의 신호와 프레임 동기신호단의 신호에 의해 제1-3래치 제어신호 및 헤드구간 제어신호를 발생하며, 상기의 제1,2래치신호를 이용하여 상기 변환기로 부터 입력되는 헤드 데이터에 있는 프레임 번호를 검출하여 EF신호에 의해 에러가 없는 하나의 프레임 번호를 검출하여 출력시킨다.The input of the serial data stage output from the DAT tape is converted into parallel data for high speed signal processing by the signal of the bit clock stage, and the first to third latch control is performed by the signal of the bit clock stage and the signal of the frame synchronization signal stage. Signal and head section control signal are generated, and the frame number in the head data input from the converter is detected using the first and second latch signals, and one frame number without error is detected by the EF signal. Output

상기에서 출력된 프레임 번호로 부터 오프셀값을 디코딩하고, 상기 디코더의 오프셀 값을 상기 제어부의 로드 오프신호로 로드시켜 오프셀 어드레스 신호를 발생하며,상기 카운터의 오프셀 어드레스와 저장기의 베이스 어드레스를 합하여 상기 메모리부의 실제 어드레스를 출력한다.Decode the off-cell value from the output frame number, and load the off-cell value of the decoder to the load off signal of the controller to generate an off-cell address signal, the off-cell address of the counter and the base address of the storage Sum to output the actual address of the memory unit.

상기 제3래치신호에 의해 상기 가산기의 출력 어드레스 신호를 래치하여 상기 하위 어드레스 신호로 구분시켜 출력하고, 상기 비트클럭단의 신호와 제어부의 헤드 구간 제어신호에 의해 상기 카운터의 카운팅 제어신호 및 메모리부(109)의 라이트 인에이블() 및 로우 칼럼어드레스 스트로브()신호를 발생하여 상기 메모리부로 데이터 입출력을 제어한다. 상기 메모리 제어부의 출력 제어신호에 의해 상기 래치회로에서 래치되는 어드레스 신호를 상,하위 어드레스신호(UPA,LOA)로 구분하여 선택한 후 상기 메모리부의 어드레스 신호로 제공한다.The output address signal of the adder is latched by the third latch signal to be divided into the lower address signals, and the output signal is divided. (109) light enable ) And low column address strobe Generates a signal to control data input / output to the memory unit. The address signal latched by the latch circuit by the output control signal of the memory controller is divided into upper and lower address signals UPA and LOA, and then provided as an address signal of the memory unit.

Description

Data Regeneration Circuit in DAT System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 회로도.1 is a circuit diagram according to the present invention.

제2도는 본 발명에 따른 타이밍도.2 is a timing diagram according to the present invention.

Claims

In the data reproducing circuit of the DAT system, a memory unit 109 for storing only data necessary for pure DAT, a micom 101 as a system controller, and address data generated from the micom 101 are received to receive a basic address value. A storage unit 102 for storing the data, a converter 112 for converting the input of the serial data stage Sout output from the DAT tape into parallel data for high-speed signal processing by the signal of the bit clock stage Bck, A controller 110 for generating the first to third latch control signals L1 to L3 and the head section control signal Hd based on the signal of the bit clock stage Bck and the frame synchronization signal terminal FR; The frame number in the head data input from the converter 112 is detected using the first and second latch signals L1 and L2 of the control unit 110, and one frame number without an error is detected by the EF signal. A detector 103 for detecting and outputting the The decoder 105 decodes the off-cell value from the frame number output from the output unit 103, and the off-cell address signal is generated by loading the off-cell value of the decoder 105 as a load off signal of the controller 110. An adder 104 which adds an actual address of the memory unit 109 by adding the counter 106, the off-cell address of the counter 106, and the base address of the storage unit 102, and the control unit 110. A latch circuit 107 for latching an output address signal of the adder 104 by the third latch signal L3 of the third latch signal L3 and dividing the output address signal into the lower address signal, and a signal and a controller of the bit clock stage Bck. The counting control signal of the counter 106 and the write enable of the memory unit 109 are performed by the head section control signal Hd of 110. ) And low column address strobe ) A memory controller 113 for generating data and controlling data input / output to the memory unit 109, and an address signal latched by the latch circuit 107 by an output control signal of the memory controller 113. And a multiplexer (108) which is divided into lower address signals (UAP, LOA) and selected and provided as address signals (A9-A7) of the memory section (109).

※ Note: The disclosure is based on the initial application.