KR940001424A - How to make programmable ROM - Google Patents

How to make programmable ROM Download PDF

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Publication number
KR940001424A
KR940001424A KR1019920010740A KR920010740A KR940001424A KR 940001424 A KR940001424 A KR 940001424A KR 1019920010740 A KR1019920010740 A KR 1019920010740A KR 920010740 A KR920010740 A KR 920010740A KR 940001424 A KR940001424 A KR 940001424A
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KR
South Korea
Prior art keywords
poly layer
region
oxide
layer
etching
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KR1019920010740A
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Korean (ko)
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KR960003500B1 (en
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김종오
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019920010740A priority Critical patent/KR960003500B1/en
Publication of KR940001424A publication Critical patent/KR940001424A/en
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Publication of KR960003500B1 publication Critical patent/KR960003500B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 프로그래머블 롬, 특히 적층게이트(Stacked-Gate)형의 EPROM또는 플래쉬 EEPROM을 제조하는 방법에 관한 것으로, 본 발명의 제조방법에 따르면, 주변회로영역의 트랜지스터는 신뢰성 등의 특성이 우수한 LDD (Lightly Doped Drain) 또는 DDD(Doubly Doped Drain)구조의 소오스/드레인을 가지 며, 메모리 셀 영 역 의 소오스/드레인구조는 소오스/드레인 방향으로는 n+구조를 이루고 기판방향으로는 DDD구조 이루도록 함으로써, 기판과의 접합 캐패시턴스를 작게 하면서도 열전자에 의한 프로그램 효율은 양호하게 유지될 수 있게 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a programmable ROM, in particular a stacked-gate type EPROM or flash EEPROM. by Lightly Doped drain) or DDD (Doubly Doped drain) said of the source / drain structure, the memory cell source / drain structure of the region is a source / drain direction, it forms an n + structure of the substrate direction is achieve DDD structure, The junction capacitance with the substrate can be made small while the program efficiency by the hot electrons can be kept good.

Description

프로그래머블 롬의 제조방법How to make programmable ROM

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 EPROM 또는 플래쉬 EEPROM 셀의 소오스/드레인 구조를 도시한 도면,2 illustrates a source / drain structure of an EPROM or flash EEPROM cell according to the present invention;

제3도는 소오스/드레인 영역에 주입되는 불순물의 농도 분포도,3 is a concentration distribution diagram of impurities injected into a source / drain region,

제4A도 내지 제4G도는 본 발명에 따른 EPROM 또는 플래쉬 EPROM의 제조공정을 도시한 도면.4A to 4G illustrate a manufacturing process of an EPROM or flash EPROM according to the present invention.

Claims (4)

적층 게이트형의 EPROM및 플래쉬 EEPROM을 포함하는 프로그래머블 롬의 제조방법에 있어서, 기판(1)위에필드산화물(2)와 제1게이트 산화막(3)을 형성시킨후 제1폴리층(4)을 1500 내지 2000Å 정도의 두께로 증착 및 도핑하는 제1단계 공정과. 셀 영역이외에 있는 제1폴리층(4)을 제거한후 열산화를 하여 제2게이트 산화막 (5)(주변회로영역) 및 폴리산화막(6) (셀 영역)을 형성하고, 제2폴리층(7) 및 질화막(8)을 순차적으로 형성시키는 제2단계 공정과, 마스크틀 이용하여 패턴형성을 하고 소정부분의 질화막(8) 및 제2폴리층(7)을 식각한 다음 50 내지 100kev정도의 에 너지로 n-이온주입을 수행하여 주변회로 영역에서만 n-형 불순물이 기판 (1)내로 침투되게 하는 제3단계 공정과, 산화물을 소정두께로 중착시킨후 비등방성 식각방법으로 소정폭의 스페이서 (9)를 형성시키는 제4단계 공정과, 마스크 작업을 통하여 주변회로 영역은 포토레지스트층(10)으로 보호하고 셀 영역만 개방시킨후, 130 내지 180kev의 고에너지 상태로 n-이온주입을 행하여 n-이온이 스페이서 (9)의 경계와 필드산화물(2)의 경계내의 기판(1)에 더 깊게 침투하게 하는 제5단계 공정과, 등방성 식각을 하여 셀 영역의 스페이서 (9)를 제거한 다음, 제2폴리층(7) 위의 질화막을 장벽충으로사용하여 제1폴리충(4)을 식각하는 제6단계 공정과, 주변 회로영 역의 포토레지스트층 (10)을 제거하고, 필요에 따라 열처리를 하여 n-영역을 열처 리한 다음 n-영역위에 n+이온주입을 행하는 제7단계 공정을 포함하는 프로그래머블 롬의 제조방법.In the method of manufacturing a programmable ROM including a stacked gate type EPROM and a flash EEPROM, the first poly layer 4 is formed by forming a field oxide 2 and a first gate oxide film 3 on the substrate 1. And a first step of depositing and doping to a thickness of about 2000 kPa. After removing the first poly layer 4 outside the cell region, thermal oxidation is performed to form the second gate oxide film 5 (peripheral circuit region) and the poly oxide film 6 (cell region), and the second poly layer 7 ) And a second step process of forming the nitride film 8 in sequence, pattern formation using a mask frame, and etching the nitride film 8 and the second poly layer 7 of a predetermined portion, followed by etching of about 50 to 100 kev. A third step of n-ion implantation with energy to allow the n-type impurities to penetrate into the substrate 1 only in the peripheral circuit region, and a spacer of a predetermined width by anisotropic etching after the oxide is deposited to a predetermined thickness. 9) After forming the fourth step process and the masking process, the peripheral circuit region is protected by the photoresist layer 10 and only the cell region is opened, and then n-ion implantation is performed in a high energy state of 130 to 180 kev. Ions are groups within the boundary of the spacer (9) and the boundary of the field oxide (2) The fifth step of deeper penetration into (1) and the isotropic etching to remove the spacers 9 in the cell region, and then using the nitride film on the second poly layer 7 as a barrier insect, A sixth step of etching (4), and removing the photoresist layer 10 in the peripheral circuit area, performing heat treatment as necessary to thermally treat the n-region, and then n + ion implantation on the n-region. A method of manufacturing a programmable ROM comprising a seventh step process. 제1항에 있어서, 상기 제1단계 공정후에, 소정의 산화물 및 질화물을 먼저 증착시키고 나서 상기 제2단계 공정을 수행하여, 제1폴리층과 제2폴리층간의 절연막이 ONO(0xide/ Nitride/ Oxide)구조를 이루게 하는 프로그래머블 롬의 제조방법.The method according to claim 1, wherein after the first step process, a predetermined oxide and nitride are first deposited and then the second step process is performed, so that the insulating film between the first poly layer and the second poly layer is turned ON (0xide / Nitride /). Method of manufacturing a programmable ROM to form an oxide structure. 제1항 또는 2항에 있어서, 상기 제1게이트 산화막(3)은 플래쉬 EEPROM을 제조할 경우 90 내지 110Å 두께로 형성하고 EPROM을 제조할 경우 200 내지 300Å 두께로 형성하는 프로그래머블 롬의 제조방법.The method of claim 1 or 2, wherein the first gate oxide layer (3) is formed to a thickness of 90 to 110 kPa when the flash EEPROM is manufactured and to 200 to 300 kPa when the EPROM is manufactured. 제1항또는 제2항에 있어서, 제2폴리층을 폴리사이드 또는 실리사이드로 형성하는 프로그래머블 롬의 제조 방법.The method of claim 1 or 2, wherein the second poly layer is formed of polysides or silicides. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920010740A 1992-06-20 1992-06-20 Process of manufacturing a programmable rom KR960003500B1 (en)

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Application Number Priority Date Filing Date Title
KR1019920010740A KR960003500B1 (en) 1992-06-20 1992-06-20 Process of manufacturing a programmable rom

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Application Number Priority Date Filing Date Title
KR1019920010740A KR960003500B1 (en) 1992-06-20 1992-06-20 Process of manufacturing a programmable rom

Publications (2)

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KR940001424A true KR940001424A (en) 1994-01-11
KR960003500B1 KR960003500B1 (en) 1996-03-14

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