KR940001398B1 - Mosfet 제조방법 - Google Patents

Mosfet 제조방법 Download PDF

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KR940001398B1
KR940001398B1 KR1019900022471A KR900022471A KR940001398B1 KR 940001398 B1 KR940001398 B1 KR 940001398B1 KR 1019900022471 A KR1019900022471 A KR 1019900022471A KR 900022471 A KR900022471 A KR 900022471A KR 940001398 B1 KR940001398 B1 KR 940001398B1
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oxide film
gate
mosfet
source
drain
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KR1019900022471A
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KR920013772A (ko
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권호엽
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

내용 없음.

Description

MOSFET 제조방법
제1도는 종래의 MOSFET 제조도.
제2도는 본 발명에 따른 MOSFET 제조도.
* 도면의 주요부분에 대한 부호의 설명
10 : P형 기판 20,30,40 : 산화막
50 : 다결정 실리콘
본 발명은 MOSFET의 제조방법에 관한 것으로, 특히 소스(Source)와 드레인(D
rain)이 형성될 부근에는 영향을 주지 않고도 채널(Channel) 부근의 농도를 조절하기에 적당하도록 한 MOSFET 제조방법에 관한 것이다.
종래에는 제1도에 도시한 바와 같이 첫째, P-웰(P-Well)이나 P형 기판(1)위에 소자격리를 위한 산화(2)를 실시한다(제1도의 (a)).
둘재, MOSFET의 문턱전압 등의 전기적 특성을 맞추고, 채널농도 조절을 위하여 브론(Voron) 이온을 주입한다(제1도의 (b)).
셋째, 게이트 산화막(3)과 다결정 실리콘(4)을 차례로 증착시킨 후 게이트를 위하여 다결정 실리콘을 정의한다(제1도의 (c))).
넷째, 소스와 드레인을 형성시킨다(제1도의 (d)).
이와 같이 종래의 MOSFET 제조방법은 MOSFET의 문턱전압 등 전기적 특성을 만족시키기 위하여 채널 이온주입을 하거나 처음부터 높은 농도의 P-웰이나 P형 기판을 사용하게 됨으로써 채널 뿐만 아니라 소스와 드레인이 형성될 부분까지도 높은 농도를 유지시키기 때문에 MOSFET가 형성되었을 때, 소스, 드레인과 기판 사이에 캐패시턴스가 큰 값을 갖는 등 MOSFET의 전기적 특성에 나쁜 영향을 주는 문제점이 있었다.
따라서 본 발명은 상기한 문제점을 개선시킨 것으로 제2도에 따라 상세히 설명하면 다음과 같다.
첫째, P-웰이나 P형 기판(10)위에 소자격리를 위한 필드산화(20)를 실시한다
(제2도의 (a)).
둘째, P형 기판(10)위에 산화막(30)을 증착시킨 후 게이트의 모양과 반대로 반대로 형성된 마스크를 이용하여 산화막을 정의한다(제2도의 (b)).
셋째, MOSFET의 문턱전압 등 전기적 특성만을 만족시키고 채널 농도만을 조절하기 위하여 브론(Boron) 이온주입을 실시한다(제2도의 (c)).
넷째, 게이트 산화막(40)을 성장시키고, 다결정 실리콘(50)을 증착시킨 후 에치백(Etch-back)을 이용하여 게이트로 사용될 다결정 실리콘만을 남김으로써 게이트 다결정 실리콘을 정의한다(제2도의 (d)).
다섯째, 소스와 드레인 등의 형성될 부분의 산화막(30)을 제거한다(제2도의 (e)).
여섯째, 게이트를 마스크로 하여 저농도 n형 이온주입하고 게이트에 측벽을 형성한 다음 다시 고농도 n형 이온주입하여 소스와 드레인을 형성시킨다(제2도의 (f)).
이와같이 본 발명은 MOSFET의 채널이 형성될 부분만 문턱전압 등 전기적 특성을 만족시키기 위한 농도로 맞추어줌으로써 소스와 드레인이 형성될 부분을 낮은 농도로 유지시키고 따라서, 소스, 드레인과 기판사이의 커패시턴스가 상당히 낮은 값을 갖는 등 트랜지스터의 전기적 특성을 개선할 수 있음은 물론 채널농도를 조절하여 소스, 드레인 접합이 채널쪽으로 들어오는 것을 막을 수 있으므로 소스, 드레인이 접합길이에 대한 영향을 줄일 수 있는 데에 효과가 있다.

Claims (1)

  1. P형 기판(10)위에 소자격리를 위한 필드산화막(20)을 형성한 후 산화막(30)을 증착시키고 게이트 형성영역의 산화막(30)을 제거하는 공정과, 노출된 기판(10)에 채널 이온주입하고 게이트 산화막(40)을 성장시킨후 다결정 실리콘을 증착하고 에치백하여 산화막(30)이 제거된 부위에 게이트 다결정 실리콘(50)을 형성하는 공정과, 산화막(30)을 제거한 후 이온주입으로 소스와 드레인을 형성시키는 공정을 포함하여 이루어지는 것을 특징으로 하는 MOSFET 제조방법.
KR1019900022471A 1990-12-29 1990-12-29 Mosfet 제조방법 KR940001398B1 (ko)

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