KR930020674A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

Info

Publication number
KR930020674A
KR930020674A KR1019920004174A KR920004174A KR930020674A KR 930020674 A KR930020674 A KR 930020674A KR 1019920004174 A KR1019920004174 A KR 1019920004174A KR 920004174 A KR920004174 A KR 920004174A KR 930020674 A KR930020674 A KR 930020674A
Authority
KR
South Korea
Prior art keywords
semiconductor device
manufacturing
trench
film
oxide film
Prior art date
Application number
KR1019920004174A
Other languages
Korean (ko)
Other versions
KR960016836B1 (en
Inventor
고재홍
김성태
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920004174A priority Critical patent/KR960016836B1/en
Publication of KR930020674A publication Critical patent/KR930020674A/en
Application granted granted Critical
Publication of KR960016836B1 publication Critical patent/KR960016836B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 트렌치형 커패시터를 구비한 반도체장치에 있어서 인접한 트레치간의 누설전류를 억제할 수 있는 반도체장치 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of suppressing leakage current between adjacent trenches and a method of manufacturing the same in a semiconductor device having a trench capacitor.

본 발명에 의하면, 트렌치형 커패시터를 구비한 적어도 2개의 메모리셀을 포함하는 반도체장치에 있어서, 상기 트렌치의 인접한 트렌치측의 내면상에 절연막이 형성되어 있음을 특징으로 하는 반도체장치가 제공되며, 또한 트렌치형 커패시터를 구비한 적어도 2개의 메모리셀을 포함하는 반도체장치의 제조방법에 있어서, 반도체기판 소정영역에 트렌치를 형성한 후 상기 트렌치의 인접한 트렌치측의 내면상에 절연막을 형성하는 공정을 포함함을 특징으로 하는 반도체장치의 제조방법이 제공된다.According to the present invention, there is provided a semiconductor device comprising at least two memory cells having a trench capacitor, wherein a semiconductor device is formed on an inner surface of an adjacent trench side of the trench. A method of manufacturing a semiconductor device including at least two memory cells having a trench capacitor, the method comprising forming a trench in a predetermined region of a semiconductor substrate and forming an insulating film on an inner surface of an adjacent trench side of the trench. A method of manufacturing a semiconductor device is provided.

따라서 본 발명에 의하면, 트렌치형 커패시터를 구비한 반도체장치에 있어서 인접한 트렌치간의 누설전류를 억제할 수 있음에 따라 보다 신뢰성 높은 반도체 디바이스의 제조가 가능하게 된다.Therefore, according to the present invention, the leakage current between adjacent trenches can be suppressed in a semiconductor device having a trench capacitor, so that a more reliable semiconductor device can be manufactured.

Description

반도체장치 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 반도체장치를 나타낸 단면도이다.2 is a cross-sectional view showing a semiconductor device according to the present invention.

제3A도 내지 제3E는 본 발명에 의한 반도체장치의 제조방법을 나타낸 공정순서도이다.3A to 3E are process flowcharts showing a method for manufacturing a semiconductor device according to the present invention.

Claims (15)

트렌치형 커패시터를 구비하는 적어도 2개의 메모리셀을 포함하는 반도체장치에 있어서, 상기 트렌치의 인접한 트렌치측의 내면상에 절연막이 형성되어 있음을 특징으로 하는 반도체장치.12. A semiconductor device comprising at least two memory cells having a trench capacitor, wherein an insulating film is formed on an inner surface of an adjacent trench side of the trench. 제1항에 있어서, 상기 절연막은 산화막임을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein said insulating film is an oxide film. 트렌치형 커패시터를 구비한 적어도 2개의 메모리셀을 포함하는 반도체장치의 제조방법에 있어서, 반도체기판 소정영역에 트렌치를 형성한 후 상기 트렌치의 인접한 트렌치측의 내면상에 절연막을 형성하는 공정을 포함함을 특징으로 하는 반도체장치의 제조방법.A method of manufacturing a semiconductor device including at least two memory cells having a trench capacitor, the method comprising forming a trench in a predetermined region of a semiconductor substrate and forming an insulating film on an inner surface of an adjacent trench side of the trench. A method of manufacturing a semiconductor device, characterized by the above-mentioned. 제3항에 있어서, 상기 트렌치의 인접한 트렌치측의 내면상에 절연막을 형성하는 공정은, 반도체기판상에 산화막을 형성하고 사진식각 공정에 의해 상기 산화막을 마스크로 하여 반도체기판 소정영역에 트렌치를 형성하는 공정; 결과물 전면에 산화방지막과 산화막을 차례로 형성한 후 상기 산화막을 활성영역 패턴으로 패터닝하는 공정; 패터닝된 산화막을 마스크로하여 상기 산화방지막을 제거하고 상기 산화막을 제거한 후 결과물을 산화하는 공정을 구비한 것을 특징으로 하는 반도체장치의 제조방법.4. The process of claim 3, wherein the step of forming an insulating film on an inner surface of an adjacent trench side of the trench comprises forming an oxide film on a semiconductor substrate and forming a trench in a predetermined region of the semiconductor substrate using the oxide film as a mask by a photolithography process. Process of doing; Forming an oxide film and an oxide film on the entire surface of the resultant and then patterning the oxide film into an active region pattern; And removing the antioxidant film using the patterned oxide film as a mask, removing the oxide film, and then oxidizing the resultant. 제4항에 있어서, 사익 절연막은 산화막임을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein the wing insulation film is an oxide film. 제4항에 있어서, 상기 산화방지막은 질화막임을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein said antioxidant film is a nitride film. 제4항에 있어서, 상기 산화방지막을 형성하는 공정전에 패드산화막을 형성하는 공정이 더 포함됨을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a pad oxide film before the step of forming the antioxidant film. 제4항에 있어서, 상기 산화공정은 로(furnace)내에서 행함을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein said oxidation process is performed in a furnace. 제4항에 있어서, 상기 산화공정에 의해 트렌치 측벽에 형성되는 산화막의 두께는 100A∼5000A임을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein the thickness of the oxide film formed on the trench sidewalls by the oxidation step is 100A to 5000A. 제4항에 있어서, 상기 산화공정에 의해 반도체기판의 필드영역상에 필드산화막이 형성됨을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein a field oxide film is formed on the field region of the semiconductor substrate by the oxidation process. 제4항에 있어서, 상기 활성영역 패턴 형성은 다층감광막법에 의해 행함을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein the active region pattern is formed by a multilayer photoresist film method. 제4항에 있어서, 상기 산화공정후에 상기 질화막을 제거한 다음 제1도전층, 유전체막 및 제2도전층을 차례로 증착하여 커패시티를 형성하는 공정이 더 포함됨을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, further comprising removing the nitride film after the oxidation process and then depositing a first conductive layer, a dielectric film, and a second conductive layer in order to form a capacity. 제12항에 있어서, 상기 제1도전층은 불순물이 도핑된 다결정실리콘, HSG다결정실리콘 또는 텅스텐으로 형성함을 특징으로 하는 반도체장치의 제조방법.The method of claim 12, wherein the first conductive layer is formed of polycrystalline silicon, HSG polycrystalline silicon, or tungsten doped with impurities. 제12항에 있어서, 상기 유전체막은로 형성함을 특징으로 하는 반도체장치의 제조방법.The method of claim 12, wherein the dielectric film The semiconductor device manufacturing method characterized in that it is formed. 제12항에 있어서, 상기 제2도전층은 불순물이 도핑된 다결정 실리콘으로 형성함을 특징으로 하는 반도체장치의 제조방법.The method of claim 12, wherein the second conductive layer is formed of polycrystalline silicon doped with impurities. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920004174A 1992-03-13 1992-03-13 Method of manufacturing a semiconductor device KR960016836B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920004174A KR960016836B1 (en) 1992-03-13 1992-03-13 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920004174A KR960016836B1 (en) 1992-03-13 1992-03-13 Method of manufacturing a semiconductor device

Publications (2)

Publication Number Publication Date
KR930020674A true KR930020674A (en) 1993-10-20
KR960016836B1 KR960016836B1 (en) 1996-12-21

Family

ID=19330359

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920004174A KR960016836B1 (en) 1992-03-13 1992-03-13 Method of manufacturing a semiconductor device

Country Status (1)

Country Link
KR (1) KR960016836B1 (en)

Also Published As

Publication number Publication date
KR960016836B1 (en) 1996-12-21

Similar Documents

Publication Publication Date Title
JPH0465548B2 (en)
KR930020676A (en) Semiconductor memory device and manufacturing method thereof
KR100255064B1 (en) Method of forming a capacitor over a semiconductor substrate
JPH05206451A (en) Mosfet and its manufacture
KR100427922B1 (en) A semiconductor device and manufacturing method thereof
KR930020581A (en) Contact hole structure and manufacturing method
KR100258880B1 (en) Method for manufacturing semiconductor device
KR930020674A (en) Semiconductor device and manufacturing method
JPS63305527A (en) Semiconductor device and manufacture thereof
JPS61225851A (en) Semiconductor device and manufacture thereof
KR100226791B1 (en) Manufacturing method of a semiconductor device
KR940022925A (en) Method for manufacturing an isolated region in a semiconductor device
KR100219055B1 (en) Forming method for contact hole of semiconductor device
JPS60160666A (en) Manufacture of semiconductor device
KR950005466B1 (en) Method of fabricating dram cell
KR980012486A (en) Method for manufacturing capacitor of semiconductor device
KR100249157B1 (en) Method for fabricating of semiconductor device
KR0172268B1 (en) Method of manufacturing semiconductor device
KR100529624B1 (en) Method for fabricating the MIM capacitor in semiconductor device
KR0164152B1 (en) Capacitor fabrication method of semiconductor device
KR100215862B1 (en) Capacitor of semiconductor device and its fabrication method
KR100239454B1 (en) Method of forming an element isolation region in a semiconductor device
KR0157975B1 (en) Stack capacitor fabrication method
KR940003049A (en) Semiconductor memory device and manufacturing method thereof
KR20020050423A (en) Method for manufacturing capacitor in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20011107

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee