KR930014888A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

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Description

Semiconductor device and manufacturing method thereof

As this is a public information case, the full text was not included.

1A is a plan view of a conventional MOS transistor, with the interlayer insulating film removed.

FIG. 1B is a cross-sectional view taken along the line 1-1 shown in FIG. 1A.

2A is a cross-sectional view showing a part of a manufacturing process of a conventional semiconductor device.

FIG. 2B is a cross sectional view showing a part of a conventional semiconductor device manufacturing process, and showing a step in which a step is generated between the semiconductor substrate and the buried insulating film.

3 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a process of forming a field oxide film on a silicon substrate.

4 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a step of forming a channel ion implantation layer.

5 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention and showing a process of forming a polycrystalline silicon layer.

6 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a step of forming a first groove.

7 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a step of forming a side wall member on the sidewall of the first groove.

8 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a step of etching a gate oxide film using a sidewall material and a SiN film as a mask.

9 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a step of forming a second groove.

FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a step of forming a silicon oxide film on the inner surface of a second groove.

FIG. 11 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing the process of forming an embedding insulating film.

12 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a step of forming a MoSi _2or3 film.

FIG. 13 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a process of providing gate electrode wiring. FIG.

14 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a step of providing lead electrode wiring.

Fig. 15 is an enlarged cross-sectional view showing the vicinity of the element isolation region of the semiconductor device according to the embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

21 silicon substrate 22 field oxide film

23 gate oxide film 24 channel ion implantation layer

25 polycrystalline silicon layer 26 SiN film

27: first groove 28: side wall material

29: second groove 30: thermal oxide film

31: inversion prevention layer, 23a, 23b embedding insulating film

32C: device isolation region 32d: side

33: MOSi _2or3 film 34a, 34b: gate electrode wiring

35: N ⁺ diffusion layer 36: inter-wire insulating film

37a: first contact hole 37b: second contact hole

38a, 38b: lead wire low pole wiring 39: channel region

39a: end

Claims (12)

A first insulating film 23 formed on the surface of the semiconductor substrate 21; A first conductive layer 25 formed on the first insulating film; A first groove 27 provided in the first conductive layer; A second groove (29) provided in the semiconductor substrate and in communication with the first groove and having a diameter smaller than that of the first groove; A second insulating film 32a formed in said first and second grooves; A second conductive layer 33 formed on said first conductive layer and said second insulating film; A gate electrode 34b provided at one end of the first and second conductive layers; And a source / drain region (35) formed in said semiconductor substrate located on both sides of said gate electrode. Forming a first insulating film on the surface of the semiconductor substrate, providing a first conductive layer on the insulating film, and providing a first groove in the conductive layer; Forming a second groove communicating with the first groove in the semiconductor substrate, the second groove having a smaller diameter than the first groove; Forming a second insulating film in the first and second grooves; Providing a second conductive layer on the first conductive layer and the second insulating film, and providing a gate electrode on one end of the first and second conductive layers; And forming source and drain regions in the semiconductor substrate located at both sides of the gate electrode. Forming a first insulating film on the surface of the semiconductor substrate, and providing a first conductive layer on the insulating film; Forming a first groove in the first conductive layer by providing a first mask material on the first conductive layer and etching the mask material as a mask; A second mask material is deposited on the first groove and the first mask material, and anisotropically etches the mask material so that the side wall of the first groove is formed of the second mask material. Installing a part; Forming a second groove in the first insulating film and the semiconductor substrate by etching the sidewall portion and the first mask material as a mask; Removing the side wall portion; Forming a second insulating film located between the upper surface and the lower surface of the first conductive layer in the first and second grooves; Removing the first mask material and providing a second full layer on the first conductive layer and the second insulating film; Providing a gate electrode by etching the first and second conductive layers; And forming source and drain regions in the semiconductor substrate located at both sides of the gate electrode. The semiconductor device according to claim 1, wherein said first conductive layer comprises polycrystalline silicon. The semiconductor device according to claim 1, wherein said second conductive layer is made of a high melting point metal. The semiconductor device according to claim 1, wherein the second conductive layer is made of silicon containing a high melting point metal. The method of manufacturing a semiconductor device according to claim 2, wherein said first conductive layer comprises polycrystalline silicon. The method of manufacturing a semiconductor device according to claim 2, wherein the second conductive layer is made of a high melting point metal. The method of manufacturing a semiconductor device according to claim 2, wherein the second conductive layer is made of silicon containing a high melting point metal. 4. The method of claim 3, wherein the second conductive layer is made of a high melting point metal. 4. The method of claim 3, wherein the second conductive layer is made of a high melting point metal. 4. The method of claim 3, wherein the second conductive layer is made of silicon containing a high melting point metal. ※ Note: The disclosure is based on the initial application.