KR930014888A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- KR930014888A KR930014888A KR1019920023672A KR920023672A KR930014888A KR 930014888 A KR930014888 A KR 930014888A KR 1019920023672 A KR1019920023672 A KR 1019920023672A KR 920023672 A KR920023672 A KR 920023672A KR 930014888 A KR930014888 A KR 930014888A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive layer
- groove
- insulating film
- forming
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1a도는 종래의 MOS 트랜지스터를 도시하는 것으로 층간 절연막을 제거한 평면도.1A is a plan view of a conventional MOS transistor, with the interlayer insulating film removed.
제1b도는 제1a도에 도시하는 1-1선에 따르는 단면도.FIG. 1B is a cross-sectional view taken along the line 1-1 shown in FIG. 1A.
제2a도는 종래의 반도체 장치의 제조 공정의 일부를 도시하는 단면도.2A is a cross-sectional view showing a part of a manufacturing process of a conventional semiconductor device.
제2b도는 종래의 반도체 장치의 제조 공정의 일부를 도시하는 것이고, 반도체 기판과 매설 절연막과의 사이에 단차가 생기는 공정을 도시하는 단면도.FIG. 2B is a cross sectional view showing a part of a conventional semiconductor device manufacturing process, and showing a step in which a step is generated between the semiconductor substrate and the buried insulating film.
제 3 도는 본 발명의 실시예에 의한 반도체장치의 제조방법을 도시하는 것으로 실리콘 기판에 필드 산화막을 형성하는 공정을 도시하는 단면도.3 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a process of forming a field oxide film on a silicon substrate.
제 4 도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로 채널 이온 주입층을 형성하는 공정을 도시하는 단면도.4 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a step of forming a channel ion implantation layer.
제 5 도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로 다결정 실리콘 층을 형성하는 공정을 도시하는 도면.5 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention and showing a process of forming a polycrystalline silicon layer.
제 6 도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로, 제 1 의 홈을 형성하는 공정을 도시하는 단면도.6 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a step of forming a first groove.
제 7 도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로 제 1 의 홈의 측벽에 측벽재를 형성하는 공정을 도시하는 단면도.7 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a step of forming a side wall member on the sidewall of the first groove.
제 8 도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로 측벽재 및 SiN막을 마스크로 하여 게이트 산화막을 에칭하는 공정을 도시하는 단면도.8 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a step of etching a gate oxide film using a sidewall material and a SiN film as a mask.
제 9 도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로 제 2 의 홈을 형성하는 공정을 도시하는 단면도.9 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a step of forming a second groove.
제10도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로 제 2 의 홈의 내면에 실리콘 산화막을 형성하는 공정을 도시하는 단면도.FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention and showing a step of forming a silicon oxide film on the inner surface of a second groove.
제11도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로 매설 절연막을 형성하는 공정을 도시하는 단면도.FIG. 11 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing the process of forming an embedding insulating film.
제12도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로, MoSi2or3막을 형성하는 공정을 도시하는 단면도.12 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a step of forming a MoSi 2or3 film.
제13도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로 게이트 전극 배선을 설치하는 공정을 도시하는 단면도.FIG. 13 is a cross-sectional view showing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a process of providing gate electrode wiring. FIG.
제14도는 본 발명의 실시예에 의한 반도체 장치의 제조방법을 도시하는 것으로, 리드 전극배선을 설치하는 공정을 도시하는 단면도.14 is a cross-sectional view showing a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention, showing a step of providing lead electrode wiring.
제15도는 본 발명의 실시예에 의한 반도체 장치의 소자 분리 영역의 근방을 도시하는 확대단면도.Fig. 15 is an enlarged cross-sectional view showing the vicinity of the element isolation region of the semiconductor device according to the embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘 기판 22 : 필드 산화막21 silicon substrate 22 field oxide film
23 : 게이트 산화막 24 : 채널 이온 주입층23 gate oxide film 24 channel ion implantation layer
25 : 다결정 실리콘층 26 : SiN막25 polycrystalline silicon layer 26 SiN film
27 : 제 1 의 홈 28 : 측벽재27: first groove 28: side wall material
29 : 제 2 의 홈 30 : 열산화막29: second groove 30: thermal oxide film
31 : 반전 방지층, 23a, 23b 매설 절연막31: inversion prevention layer, 23a, 23b embedding insulating film
32C : 소자 분리 영역 32d : 측면32C: device isolation region 32d: side
33 : MOSi2or3막 34a, 34b : 게이트 전극 배선33: MOSi 2or3 film 34a, 34b: gate electrode wiring
35 : N+확산층 36 : 배선간 절연막35: N + diffusion layer 36: inter-wire insulating film
37a : 제 1 의 콘택트홀 37b : 제 2 의 콘택트 홀37a: first contact hole 37b: second contact hole
38a, 38b : 리드선 저극 배선 39 : 채널영역38a, 38b: lead wire low pole wiring 39: channel region
39a : 단부39a: end
Claims (12)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3325742A JPH05160254A (en) | 1991-12-10 | 1991-12-10 | Semiconductor device and production thereof |
JP91-325742 | 1991-12-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930014888A true KR930014888A (en) | 1993-07-23 |
KR960006973B1 KR960006973B1 (en) | 1996-05-25 |
Family
ID=18180149
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920023672A KR960006973B1 (en) | 1991-12-10 | 1992-12-09 | Semiconductor device and the manufacturing method |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH05160254A (en) |
KR (1) | KR960006973B1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0714916A (en) * | 1993-06-22 | 1995-01-17 | Nec Corp | Isolation structure of mos field-effect transistor and its manufacture |
JP4541980B2 (en) * | 2005-06-27 | 2010-09-08 | シャープ株式会社 | Semiconductor device |
-
1991
- 1991-12-10 JP JP3325742A patent/JPH05160254A/en active Pending
-
1992
- 1992-12-09 KR KR1019920023672A patent/KR960006973B1/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR960006973B1 (en) | 1996-05-25 |
JPH05160254A (en) | 1993-06-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR860001490A (en) | Vertical MOSFET and its manufacturing method | |
KR940019013A (en) | High voltage transistor | |
KR19980084710A (en) | Mospet device and method of manufacturing the same | |
KR19990057943A (en) | Contact hole formation method of semiconductor device | |
US6323110B2 (en) | Structure and fabrication process of silicon on insulator wafer | |
KR960039222A (en) | Semiconductor device and manufacturing method | |
EP0008903A1 (en) | Semiconductor integrated circuit device | |
KR960043167A (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
KR920022562A (en) | Semiconductor Integrated Circuit Manufacturing Method | |
KR0120572B1 (en) | Semiconductor device and manufacture of the same | |
KR100871976B1 (en) | Semiconductor device and method for fabricating the same | |
KR940002952A (en) | Semiconductor device and manufacturing method thereof | |
KR930014888A (en) | Semiconductor device and manufacturing method thereof | |
JP2729422B2 (en) | Semiconductor device | |
JP5220988B2 (en) | Semiconductor device | |
KR900007904B1 (en) | Method of manufacturing semiconductor device | |
KR20010053237A (en) | Field effect transistors, integrated circuitry, methods of forming field effect transistor gates, and methods of forming integrated circuitry | |
KR960042931A (en) | Manufacturing Method of Semiconductor Device Having SOI Structure | |
KR19980067670A (en) | Double gate transistor manufacturing method | |
KR960009991B1 (en) | Field effect transistor manufacturing process | |
JPH0481339B2 (en) | ||
KR0172463B1 (en) | Mos transistor and its fabrication | |
KR100291517B1 (en) | SIO structure semiconductor integrated circuit and its manufacturing method | |
KR100515075B1 (en) | Method of forming buried wiring of semiconductor device | |
KR100247635B1 (en) | Method for manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
NORF | Unpaid initial registration fee |