KR100291517B1 - SIO structure semiconductor integrated circuit and its manufacturing method - Google Patents
SIO structure semiconductor integrated circuit and its manufacturing method Download PDFInfo
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- KR100291517B1 KR100291517B1 KR1019980059159A KR19980059159A KR100291517B1 KR 100291517 B1 KR100291517 B1 KR 100291517B1 KR 1019980059159 A KR1019980059159 A KR 1019980059159A KR 19980059159 A KR19980059159 A KR 19980059159A KR 100291517 B1 KR100291517 B1 KR 100291517B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
본 발명은 SOI 구조의 반도체 집적회로 및 그 제조방법을 개시한다. 개시된 본 발명은, 실리콘 기판, 매몰 절연층 및 제 1 도전형의 불순물을 포함하는 반도체층이 순차적으로 적층된 SOI 기판과, 상기 SOI 기판의 반도체층 소정 부분에 형성되며, 액티브 영역을 한정하는 필드 산화막과, 상기 반도체층의 소정 부분에 형성되는 게이트 절연막을 포함하는 게이트 전극과, 상기 게이트 전극 양측의 반도체층에 형성되는 제 2 도전형의 소오스, 드레인 영역과, 상기 소오스 또는 드레인 영역 일측의 액티브 영역에 형성되는 제 1 도전형의 기판 콘택부와, 상기 반도체층 상부에 형성되는 층간 절연막과, 상기 층간 절연막내에 형성되고, 소오스 영역, 드레인 영역, 기판 콘택부의 소정 부분이 노출시키는 콘택홀, 및 상기 콘택홀내에 형성되어, 노출된 소오스 영역, 드레인 영역 및 기판 콘택부와 각각 콘택되는 소오스 전극, 드레인 전극 및 기판 전극을 포함하며, 상기 각각 콘택홀은 상기 층간 절연막 및 반도체층을 관통하여, 상기 매몰 절연층의 소정 부분이 오픈되도록 형성되고, 상기 콘택홀 내측벽에는 상기 콘택홀이 노출시키는 영역과 동일한 타입의 불순물 영역이 배치되어 있는 것을 특징으로 한다.The present invention discloses a semiconductor integrated circuit having an SOI structure and a method of manufacturing the same. Disclosed is a SOI substrate in which a silicon substrate, a buried insulating layer, and a semiconductor layer including impurities of a first conductivity type are sequentially stacked, and a field formed in a predetermined portion of a semiconductor layer of the SOI substrate and defining an active region. A gate electrode including an oxide film and a gate insulating film formed on a predetermined portion of the semiconductor layer, a source and a drain region of a second conductivity type formed in the semiconductor layers on both sides of the gate electrode, and an active portion on one side of the source or drain region A first contact type substrate contact portion formed in the region, an interlayer insulating film formed on the semiconductor layer, a contact hole formed in the interlayer insulating film, and exposed by a predetermined portion of the source region, the drain region, and the substrate contact portion; A source electrode and a drain formed in the contact hole and contacting the exposed source region, the drain region, and the substrate contact portion, respectively; A contact hole is formed to penetrate the interlayer insulating film and the semiconductor layer so that a predetermined portion of the buried insulating layer is opened, and the contact hole is exposed on the inner wall of the contact hole; The impurity regions of the same type are arranged.
Description
본 발명은 에스오아이(silicon on insulator, 이하 SOI)구조의 반도체 집적회로 및 그 제조방법에 관한 것으로, 보다 구체적으로는 SOI 기판에 형성되는 모스 트랜지스터의 신호 지연을 방지할 수 있는 SOI 구조의 반도체 집적회로 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a silicon on insulator (SOI) structure and a method of manufacturing the same. More specifically, a semiconductor integrated circuit having an SOI structure capable of preventing signal delay of a MOS transistor formed on an SOI substrate. A circuit and a method of manufacturing the same.
반도체 집적회로, 특히 CMOS-LSI는 고속화와 집적도의 향상이 지속적으로 요구되고 있다.Semiconductor integrated circuits, in particular CMOS-LSI, are constantly required to increase in speed and density.
현재까지의 성능 향상은 주로 스케일링(scaling)으로 달성할 수 있었다. 서브 마이크론까지는 일정의 전원 전압로 스케일링을 이룰수 있었기 때문에 동작 속도도 큰폭으로 향상시키는 것이 가능하였다. 그러나, 서브 마이크론 이하에서는 전원 전압도 저하되기 때문에, 단순 스케일링 만으로는 속도의 향상을 달성할 수 없다.So far, performance gains have been achieved primarily by scaling. Up to submicrons could be scaled to a constant power supply voltage, which significantly improved the operating speed. However, below the submicron, the power supply voltage is also lowered, so that the improvement in speed cannot be achieved by simple scaling alone.
이에따라, 이러한 문제점을 해결하기 위하여 새로운 기술의 개발이 계속되고 있으며, 그 중 하나로 절연체층 상에 반도체 소자를 형성하는 반도체층이 형성된 즉, SOI 구조가 제안되었다.Accordingly, in order to solve such a problem, development of a new technology is continued, and one of them has been proposed a SOI structure in which a semiconductor layer for forming a semiconductor device is formed on an insulator layer.
도 1은 종래 기술에 다른 SOI 구조의 반도체 집적 회로의 일예를 나타낸 단면도이다.1 is a cross-sectional view showing an example of a semiconductor integrated circuit having an SOI structure according to the prior art.
종래에는 도 1에 도시된 바와 같이, 실리콘 기판(1) 상에 매몰 절연층(2)과 예를들어, P 타입의 반도체층(3)이 순차적으로 적층된다. 이 반도체층(3)의 소정 부분에는 필드 산화막(4)이 형성되어, 액티브 영역이 한정된다. 액티브 영역의 소정 부분에는 게이트 절연막(5) 및 게이트 전극(6)이 배치되고, 게이트 전극(6) 양측의 액티브 영역에는 고농도 불순물이 이온 주입되어, 소오스, 드레인 영역(7a,7b)이 형성된다. 그리고, 소오스 영역(7a) 또는 드레인 영역(7b)의 일측에는 반도체층(3)의 플로팅을 방지하기 위하여, 기판 콘택부(8)가 배치된다.In the related art, as shown in FIG. 1, a buried insulating layer 2 and, for example, a P type semiconductor layer 3 are sequentially stacked on the silicon substrate 1. A field oxide film 4 is formed in a predetermined portion of the semiconductor layer 3 to define an active region. A gate insulating film 5 and a gate electrode 6 are disposed in a predetermined portion of the active region, and highly-concentrated impurities are ion-implanted in the active regions on both sides of the gate electrode 6 to form source and drain regions 7a and 7b. . In order to prevent the semiconductor layer 3 from floating on one side of the source region 7a or the drain region 7b, the substrate contact portion 8 is disposed.
반도체층(3) 상부에는 층간 절연막(9)이 형성되고, 소오스 영역(7a), 드레인 영역(7b) 및 기판 콘택부(8)이 오픈되도록 층간 절연막(9)의 소정 부분이 식각되어, 콘택홀이 형성된다.An interlayer insulating film 9 is formed on the semiconductor layer 3, and a predetermined portion of the interlayer insulating film 9 is etched to open the source region 7a, the drain region 7b, and the substrate contact portion 8. Holes are formed.
노출된 소오스 영역(7a), 드레인 영역(7b) 및 기판 콘택부(8)와 콘택되도록 콘택홀내에 베리어 금속막(10) 및 주 금속막(11)로 된 소오스, 드레인 전극(12a,12b) 및 기판 전극(12c)이 형성된다.The source and drain electrodes 12a and 12b formed of the barrier metal film 10 and the main metal film 11 in the contact hole so as to be in contact with the exposed source region 7a, drain region 7b, and substrate contact portion 8. And the substrate electrode 12c is formed.
이러한 SOI 구조의 모스 트랜지스터는 확산층의 용량이 극도로 작게 되고, 실리콘층의 두께를 100nm 이하로 하는 경우 온 전류를 증대시킬 수 있다는 장점이 있다.The MOS transistor of the SOI structure has an advantage that the capacity of the diffusion layer is extremely small, and the on-current can be increased when the thickness of the silicon layer is 100 nm or less.
그러나, SOI 구조의 반도체 집적회로는 다음의 문제점이 있다.However, the semiconductor integrated circuit of the SOI structure has the following problems.
먼저, 상기한 SOI 구조 모스 트랜지스터의 소오스, 드레인 영역(7a,7b)은 그것의 저면이 P타입 불순물 특성을 갖는 반도체층(3)과 접촉되어 있으므로, 접합 캐패시턴스가 증가하게 된다. 이에따라, 모스 트랜지스터의 신호 전달 시간이 지체된다.First, since the source and drain regions 7a and 7b of the SOI structure MOS transistor are in contact with the semiconductor layer 3 having a P-type impurity characteristic, the junction capacitance is increased. As a result, the signal transfer time of the MOS transistor is delayed.
또한, 반도체 소자의 집적도가 증가됨에 따라, 모스 트랜지스터의 접합 영역 및 기판 콘택부의 면적 또한, 상당히 감소되는 추세이다. 이에따라, 소오스, 드레인 및 기판 전극의 콘택 면적이 이에 비례하여 감소되므로, 접촉 저항이 상당히 증가된다. 이로 인하여, 신호 전달 시간이 상당히 지연된다.In addition, as the degree of integration of semiconductor elements increases, the area of the junction region and the substrate contact portion of the MOS transistor also tends to decrease considerably. As a result, the contact area of the source, drain, and substrate electrodes is reduced in proportion, thereby increasing the contact resistance considerably. As a result, the signal propagation time is significantly delayed.
따라서, 본 발명의 목적은 상기한 종래의 문제점을 해결하기 위한 것으로, 소오스, 드레인 영역의 접합 캐패시턴스를 감소시켜서 모스 트랜지스터의 신호 전달 특성을 개선할 수 있는 SOI 구조의 반도체 집적회로를 제공하는 것이다.Accordingly, an object of the present invention is to provide a semiconductor integrated circuit having an SOI structure capable of improving signal transmission characteristics of a MOS transistor by reducing the junction capacitance of the source and drain regions.
또한, 본 발명의 다른 목적은, 면적을 늘이지 않는 범위에서 소오스, 드레인 및 기판 콘택부와, 소오스, 드레인 및 기판 콘택부 각각과 콘택되는 전극들간의 콘택 면적을 증대시키어 콘택 저항을 낮출 수 있는 SOI 구조의 반도체 집적회로를 제공하는 것이다.In addition, another object of the present invention is to increase the contact area between the source, drain and substrate contact portion, and the electrodes that are in contact with each of the source, drain and substrate contact portions within a range that does not increase the area, thereby lowering the contact resistance. A semiconductor integrated circuit having an SOI structure is provided.
또한, 본 발명의 또 다른 목적은 상기한 SOI 구조의 반도체 집적회로 제조방법을 제공하는 것이다.In addition, another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit of the SOI structure described above.
도 1은 일반적인 SOI 반도체 소자의 단면도.1 is a cross-sectional view of a typical SOI semiconductor device.
도 2a 내지 도 2e는 본 발명의 일실시예에 따른 SOI 구조의 반도체 집적 회로 및 그 제조방법.2A to 2E illustrate a semiconductor integrated circuit having a SOI structure and a method of manufacturing the same according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
20 - 실리콘 기판 21 - 매몰 절연층20-silicon substrate 21-investment insulation layer
22 - 반도체층 23 - 필드 산화막22-semiconductor layer 23-field oxide film
24 - 게이트 산화막 25 - 게이트 전극24-gate oxide 25-gate electrode
26a - 소오스 영역 26b - 드레인 영역26a-source region 26b-drain region
27 - 기판 콘택부 28 - 층간 절연막27-substrate contact portion 28-interlayer insulating film
29,31 - 레지스트 패턴 30 - 제 1 측벽 불순물 영역29,31-Resist Pattern 30-First Sidewall Impurity Region
32 - 제 2 측벽 불순물 영역 34 - 베리어 금속막32-second sidewall impurity region 34-barrier metal film
35 - 주 금속막 36a - 소오스 전극35-main metal film 36a-source electrode
36b - 드레인 전극 36c - 기판 전극36b-drain electrode 36c-substrate electrode
상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 견지에 따르면, 본 발명은 실리콘 기판, 매몰 절연층 및 제 1 도전형의 불순물을 포함하는 반도체층이 순차적으로 적층된 SOI 기판과, 상기 SOI 기판의 반도체층 소정 부분에 형성되며, 액티브 영역을 한정하는 필드 산화막과, 상기 반도체층의 소정 부분에 형성되는 게이트 절연막을 포함하는 게이트 전극과, 상기 게이트 전극 양측의 반도체층에 형성되는 제 2 도전형의 소오스, 드레인 영역과, 상기 소오스 또는 드레인 영역 일측의 액티브 영역에 형성되는 제 1 도전형의 기판 콘택부와, 상기 반도체층 상부에 형성되는 층간 절연막과, 상기 층간 절연막내에 형성되고, 소오스 영역, 드레인 영역, 기판 콘택부의 소정 부분이 노출시키는 콘택홀, 및 상기 콘택홀내에 형성되어, 노출된 소오스 영역, 드레인 영역 및 기판 콘택부와 각각 콘택되는 소오스 전극, 드레인 전극 및 기판 전극을 포함하며, 상기 각각 콘택홀은 상기 층간 절연막, 실리콘층을 관통하여, 상기 매몰 절연층의 소정 부분이 오픈되도록 형성되고, 상기 콘택홀 내측벽에는 상기 콘택홀이 노출시키는 영역과 동일한 타입의 불순물 영역이 배치되어 있는 것을 특징으로 한다.In order to achieve the above object of the present invention, according to one aspect of the present invention, the present invention is a silicon substrate, a buried insulating layer and a SOI substrate in which a semiconductor layer comprising a first conductive type of impurities are sequentially stacked; A second region formed on a semiconductor layer predetermined portion of the SOI substrate and including a field oxide film defining an active region, a gate electrode including a gate insulating film formed on a predetermined portion of the semiconductor layer, and a semiconductor layer on both sides of the gate electrode. A conductive source and drain region, a first conductive substrate contact portion formed in an active region on one side of the source or drain region, an interlayer insulating film formed on the semiconductor layer, and an interlayer insulating film, A region, a drain region, a contact hole exposed by a predetermined portion of the substrate contact portion, and a source region formed in the contact hole and exposed; And a source electrode, a drain electrode, and a substrate electrode respectively contacting the phosphorus region and the substrate contact portion, wherein each of the contact holes penetrates the interlayer insulating layer and the silicon layer to open a predetermined portion of the buried insulating layer. An impurity region of the same type as that of the region exposed by the contact hole is disposed on the inner wall of the contact hole.
본 발명의 다른 견지에 의하면, 실리콘 기판, 매몰 절연층 및 제 1 도전형의 반도체층이 적층된 SOI 기판을 제공하는 단계와, 상기 반도체층의 소정 부분에 필드 산화막을 형성하는 단계와, 상기 반도체층의 소정 부분에 게이트 전극을 형성하는 단계와, 상기 게이트 전극 양측의 반도체층에 제 2 전도형의 불순물을 이온 주입하여, 소오스, 드레인 영역을 형성하는 단계와, 상기 소오스 영역 또는 드레인 영역의 일측에 제 1 전도형의 기판 콘택부를 형성하는 단계와, 상기 반도체층 상부에 층간 절연막을 형성하는 단계와, 상기 소오스 영역, 드레인 영역, 기판 콘택부를 노출시킴과 동시에 그 하부의 매몰 절연층이 노출되도록, 반도체층을 식각하여 콘택홀을 형성하는 단계와, 상기 각각의 콘택홀 내벽 및 저면에 소정의 불순물을 주입하여 제 1 및 제 2 측벽 불순물 영역을 형성하는 단계, 및 상기 소오스 영역, 드레인 영역 및 기판 콘택부가 노출된 각각의 콘택홀 내에 소오스 전극, 드레인 전극 및 기판 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a SOI substrate in which a silicon substrate, a buried insulating layer, and a first conductive semiconductor layer are stacked, forming a field oxide film on a predetermined portion of the semiconductor layer, and Forming a gate electrode in a predetermined portion of the layer, ion implanting a second conductivity type impurity into the semiconductor layers on both sides of the gate electrode to form a source and a drain region, and one side of the source or drain region Forming a first contact type substrate contact portion in the semiconductor substrate, forming an interlayer insulating layer on the semiconductor layer, exposing the source region, the drain region, and the substrate contact portion, and at the same time, to expose the buried insulating layer thereunder. Forming a contact hole by etching the semiconductor layer, and implanting a predetermined impurity into the inner wall and the bottom of each of the contact hole to form first and second sidewalls. Forming an impurity region, and forming a source electrode, a drain electrode, and a substrate electrode in each contact hole to which the source region, the drain region, and the substrate contact portion are exposed.
본 발명에 의하면, SOI 구조의 반도체 집적 회로에서, 소오스, 드레인 영역의 저면이 매몰 절연층에 닿도록 형성하여, 소오스, 드레인 영역의 접합 캐패시턴스를 줄인다.According to the present invention, in a semiconductor integrated circuit having an SOI structure, the bottom surfaces of the source and drain regions are formed to contact the buried insulating layer, thereby reducing the junction capacitance of the source and drain regions.
또한, 소오스, 드레인 영역 및 기판 콘택부를 매몰 절연층까지 연장배치시키어, 전극들과의 접촉 면적을 증대시키므로써, 접촉 저항을 감소시킨다.In addition, the source, drain region and substrate contact portions are extended to the buried insulating layer, thereby increasing the contact area with the electrodes, thereby reducing the contact resistance.
이에따라, 모스 트랜지스터의 신호 전달 시간이 향상된다As a result, the signal transfer time of the MOS transistor is improved.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2a 내지 도 2e는 본 발명의 일실시예에 따른 SOI 구조의 반도체 집적회로 제조방법을 설명하기 위한 각 공정별 단면도이다.2A through 2E are cross-sectional views of respective processes for describing a method for fabricating a semiconductor integrated circuit having an SOI structure according to an embodiment of the present invention.
먼저, 도 2a를 참조하여, 실리콘 기판(20), 매몰 절연층(21) 및 반도체층(22)이 순차적으로 적층된 SOI 기판(100)이 제공된다. 여기서, 반도체층(22)은 소정의 불순물 타입, 예를들어, P형의 불순물이 포함되어 있다. 이때, SOI 기판(100)은 공지된 본딩 방식, 또는 SIMOX(Separation by Implanted OXygen) 방식으로 형성될 수 있다. 이때, 매몰 절연층(21)은 실리콘 산화막 또는 실리콘 질화막일 수 있다. 그다음, 반도체층(22)의 소정 부분에 공지의 로코스(LOCOS) 방법, 트랜치(trench) 방법등을 이용하여 필드 산화막(23)을 형성하여, 액티브 영역을 한정한다. 그런다음, 액티브 영역의 소정 부분에 게이트 절연막(24)과 게이트 전극(25)을 형성한다. 이어서, 게이트 전극(25) 양측의 액티브 영역에 반도체층(22)과 반대 타입의 불순물 예를들어, N형 불순물을 이온 주입하여, 소오스, 드레인 영역(26a, 26b)을 형성한다. 그리고나서, 소오스 또는 드레인 영역(26a,26b) 일측의 액티브 영역에 반도체층(22)과 동일한 불순물 예를들어, 고농도 P형의 불순물을 이온 주입하여, 기판 콘택부(27)를 형성한다. 여기서, 기판 콘택부(27)는 반도체층(22)이 플로팅되는 것을 방지하는 역할을 한다. 이때, 소오스, 드레인 영역(26a,26b) 및 기판 콘택부(27)의 면적은 종래의 면적과 동일하게 형성된다.First, referring to FIG. 2A, an SOI substrate 100 in which a silicon substrate 20, a buried insulating layer 21, and a semiconductor layer 22 are sequentially stacked is provided. Here, the semiconductor layer 22 contains a predetermined impurity type, for example, P-type impurities. In this case, the SOI substrate 100 may be formed by a known bonding method or a Separation by Implanted Oxygen (SIMOX) method. In this case, the buried insulating layer 21 may be a silicon oxide film or a silicon nitride film. Next, the field oxide film 23 is formed in a predetermined portion of the semiconductor layer 22 by using a known LOCOS method, a trench method, or the like to define the active region. Then, the gate insulating film 24 and the gate electrode 25 are formed in a predetermined portion of the active region. Subsequently, an ion, for example, an N-type impurity opposite to the semiconductor layer 22 is implanted into the active regions on both sides of the gate electrode 25 to form the source and drain regions 26a and 26b. Then, the same impurity as the semiconductor layer 22, for example, a high concentration P-type impurity is ion-implanted into the active region on one side of the source or drain regions 26a and 26b to form the substrate contact portion 27. Here, the substrate contact portion 27 serves to prevent the semiconductor layer 22 from floating. At this time, the areas of the source, the drain regions 26a and 26b and the substrate contact portion 27 are formed to be the same as the conventional areas.
그 다음, 반도체층(22) 상부에 층간 절연막(28)을 형성한다. 그후 소오스, 드레인 영역(26a,26b) 및 기판 콘택부(27)의 소정 부분이 노출되도록 층간 절연막(28)을 형성하여, 제 1 콘택홀(h1)을 형성한다. 이때, 제 1 콘택홀(h1)의 사이즈는 종래의 콘택홀 사이즈와 동일하게 형성한다.Next, an interlayer insulating film 28 is formed over the semiconductor layer 22. Thereafter, the interlayer insulating film 28 is formed to expose the source, the drain regions 26a and 26b and the predetermined portion of the substrate contact portion 27, thereby forming the first contact hole h1. At this time, the size of the first contact hole h1 is formed to be the same as the conventional contact hole size.
그후, 도 2b에 도시된 바와 같이, 제 1 콘택홀(h1)을 마스크로 하여, 노출된 소오스, 드레인 영역(26a,26b) 및 기판 콘택부(27) 및 그 하부의 반도체층(22)을 식각하여, 매몰 절연층(21)이 노출되도록 제 2 콘택홀(h2)을 형성한다.Then, as shown in FIG. 2B, the exposed source, drain regions 26a and 26b and the substrate contact portion 27 and the underlying semiconductor layer 22 are formed using the first contact hole h1 as a mask. By etching, the second contact hole h2 is formed to expose the buried insulating layer 21.
그리고나서, 도 2c에 도시된 바와 같이, 소오스 및 드레인 영역(26a,26b)의 제 2 콘택홀(h2)이 노출되도록 공지의 포토리소그라피 공정에 의하여 제 1 레지스트 패턴(29)을 형성한다. 그리고나서, 노출된 제 2 콘택홀(h2) 내측벽에 소오스, 드레인 영역(26a,26b)과 동일한 타입을 갖는 불순물을 이온 주입하여, 제 1 측벽 불순물 영역(30)을 형성한다. 이때, 제 1 측벽 불순물 영역(30)을 형성하기 위한 불순물 이온 주입은 경사 방향으로 틸트시켜가면서 이온 주입한다. 이에따라, 소오스, 드레인 영역(26a,26b)이 매몰 절연층(21)에 까지 연장되고, 그 저면은 매몰 절연층(21)에 닿게 된다.Then, as illustrated in FIG. 2C, the first resist pattern 29 is formed by a known photolithography process so that the second contact holes h2 of the source and drain regions 26a and 26b are exposed. Then, an impurity having the same type as the source and drain regions 26a and 26b is ion-implanted into the exposed inner wall of the second contact hole h2 to form the first sidewall impurity region 30. At this time, the impurity ion implantation for forming the first sidewall impurity region 30 is ion implanted while tilting in the oblique direction. As a result, the source and drain regions 26a and 26b extend up to the buried insulating layer 21, and the bottom thereof contacts the buried insulating layer 21.
그후, 제 1 레지스트 패턴(29)을 공지의 방식으로 제거한다음, 도 2d에 도시된 바와 같이, 기판 콘택부(27)가 노출되도록 제 2 레지스트 패턴(31)을 형성한다. 그리고나서, 노출된 기판 콘택부(27)를 노출시키는 제 2 콘택홀(h2)의 내측벽에 기판 콘택부(27)와 동일 타입의 불순물을 주입하여, 제 2 측벽 불순물 영역(32)을 형성한다. 이때도 마찬가지로, 제 2 측벽 불순물 영역(32)의 형성으로 기판 콘택부(27)가 매몰 절연층(21)까지 연장되고, 기판 콘택부(27)의 저면이 매몰 절연층(22)에 닿게 된다.Thereafter, the first resist pattern 29 is removed in a known manner, and then, as shown in FIG. 2D, the second resist pattern 31 is formed to expose the substrate contact portion 27. Then, an impurity of the same type as the substrate contact portion 27 is implanted into the inner wall of the second contact hole h2 exposing the exposed substrate contact portion 27 to form the second sidewall impurity region 32. do. At this time as well, the formation of the second sidewall impurity region 32 extends the substrate contact portion 27 to the buried insulating layer 21, and the bottom surface of the substrate contact portion 27 contacts the buried insulating layer 22. .
그리고나서, 제 2 레지스트 패턴(31)을 제거한다음, 도 2e에 도시된 바와 같이, 결과물 상부에 제 2 콘택홀내의 제 1 및 제 2 측벽 불순물 영역(30,32)과 콘택되도록 베리어 금속막(34)과 주 금속막(35)을 순차적으로 적층한다음, 소정 부분 패터닝하여, 소오스 전극(36a), 드레인 전극(36b) 및 기판 전극(36c)을 형성한다.Then, after removing the second resist pattern 31, as shown in FIG. 2E, the barrier metal film (not shown) is in contact with the first and second sidewall impurity regions 30 and 32 in the second contact hole on the resultant. 34 and the main metal film 35 are sequentially stacked, and then patterned to be partially patterned to form the source electrode 36a, the drain electrode 36b, and the substrate electrode 36c.
이와같은 본 발명은 소오스, 드레인 영역(26a,26b) 및 기판 콘택부(27)가 매몰 절연층(21)까지 연장되고, 그것들이 저면이 매몰 절연층(21)에 닿게된다.In the present invention as described above, the source, the drain regions 26a and 26b and the substrate contact portion 27 extend up to the buried insulating layer 21, and the bottom surface thereof contacts the buried insulating layer 21.
이에따라, 매몰 절연층(21)에 닿는 면적만큼 소오스, 드레인 영역의 접합 캐패시턴스가 감소되어, 신호 지연을 방지할 수 있다.As a result, the junction capacitance of the source and drain regions is reduced by the area of the buried insulating layer 21, thereby preventing the signal delay.
또한, 소오스, 드레인 영역(26a,26b) 및 기판 콘택부(27)가 매몰 절연층(21)까지 연장되어 있으므로, 소오스, 드레인 영역(26a,26b) 및 기판 콘택부(27)와 소오스, 드레인 전극(36a,36b) 및 기판 전극(36c)이 접촉되는 표면적이 증대된다. 이에따라, 접촉 저항이 감소되어, 신호 지연을 한층더 방지할 수 있다.In addition, since the source, drain regions 26a and 26b and the substrate contact portion 27 extend to the buried insulating layer 21, the source, drain regions 26a and 26b and the substrate contact portion 27 and the source and drain are The surface area where the electrodes 36a and 36b and the substrate electrode 36c come into contact with each other is increased. Accordingly, the contact resistance is reduced, which can further prevent signal delay.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, SOI 구조의 반도체 집적 회로에서, 소오스, 드레인 영역의 저면이 매몰 절연층에 닿도록 형성하여, 소오스, 드레인 영역의 접합 캐패시턴스를 줄인다.As described in detail above, according to the present invention, in the semiconductor integrated circuit of the SOI structure, the bottom surface of the source and drain regions is formed to contact the buried insulating layer, thereby reducing the junction capacitance of the source and drain regions.
또한, 소오스, 드레인 영역 및 기판 콘택부를 매몰 절연층까지 연장배치시키어, 전극들과의 접촉 면적을 증대시키므로써, 접촉 저항을 감소시킨다.In addition, the source, drain region and substrate contact portions are extended to the buried insulating layer, thereby increasing the contact area with the electrodes, thereby reducing the contact resistance.
이에따라, 모스 트랜지스터의 신호 전달 시간이 향상된다.As a result, the signal transfer time of the MOS transistor is improved.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (8)
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980059159A KR100291517B1 (en) | 1998-12-28 | 1998-12-28 | SIO structure semiconductor integrated circuit and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100291517B1 (en) |
-
1998
- 1998-12-28 KR KR1019980059159A patent/KR100291517B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000042867A (en) | 2000-07-15 |
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