KR930014599A - Current Reduction Circuit of Semiconductor Memory - Google Patents

Current Reduction Circuit of Semiconductor Memory Download PDF

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Publication number
KR930014599A
KR930014599A KR1019910025749A KR910025749A KR930014599A KR 930014599 A KR930014599 A KR 930014599A KR 1019910025749 A KR1019910025749 A KR 1019910025749A KR 910025749 A KR910025749 A KR 910025749A KR 930014599 A KR930014599 A KR 930014599A
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KR
South Korea
Prior art keywords
circuit
eqp
semiconductor memory
current reduction
reduction circuit
Prior art date
Application number
KR1019910025749A
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Korean (ko)
Inventor
이종석
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910025749A priority Critical patent/KR930014599A/en
Publication of KR930014599A publication Critical patent/KR930014599A/en

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Abstract

본 발명은 반도체 메모리의 전류감소회로에 관한 것으로, 입력단(1)과, 어드레스 버퍼(2)와, EQP신호발생회로(10)와, 프리 디코더회로(9)와, X-디코더(11)를 구비하여, 입력으로 들어오는 신호를 수신하여, 일정기간지연시킨후, EQP신호를 발생시켜서, 워드라인이 선택되고, 판독동작이 완료된후, 상기 EQP신호로 다시 워드라인을 오프시킴으로 판독동작완료후 셀에 흐르는 전류를 방지하여 전류소비를 감소시키는 반도체 메모리의 전류감소회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current reduction circuit of a semiconductor memory, and includes an input stage 1, an address buffer 2, an EQP signal generation circuit 10, a predecoder circuit 9, and an X-decoder 11. After receiving the signal coming into the input, delaying for a certain period of time, generates the EQP signal, the word line is selected, after the read operation is completed, the word line is turned off again by the EQP signal, the cell after the completion of the read operation The present invention relates to a current reduction circuit of a semiconductor memory which prevents current flowing through and reduces current consumption.

Description

반도체 메모리의 전류감소회로Current Reduction Circuit of Semiconductor Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명을 적용한 위드라인 선택회로를 도시한 도면.3 is a view showing a withline selection circuit to which the present invention is applied.

제4도는 본 발명이 적용된 회로에 대한 신호파형도.4 is a signal waveform diagram of a circuit to which the present invention is applied.

Claims (3)

반도체 메모리의 전류감소회로에 있어서, 입력단(1)과, 입력단(1)의 출력을 받아 프리-디코더(9)로 출력시키는 어드레스 버퍼(2)와, EQP펄스를 발생시키는 EQP신호 발생회로(10)와, 어드레스 버퍼(2)의 출력과 EQP발생회로(10)로부터의 EQP펄스를 입력으로 받아 WL을 선택하기 위한 X-디코더회로(11)로 신호를 보내는 NAND게이트와 인버터의 조합으로 이루어진 프리-디코더회로(9)와, WL을 선택하기 위한 X-디코더회로(11)를 구비하는 것을 특징으로 하는 반도체 메모리의 전류감소회로.In the current reduction circuit of the semiconductor memory, the input terminal 1, the address buffer 2 which receives the output of the input terminal 1 and outputs it to the pre-decoder 9, and the EQP signal generation circuit 10 which generates the EQP pulses. ) And a combination of a NAND gate and an inverter, which receives the output of the address buffer 2 and the EQP pulses from the EQP generation circuit 10 as inputs and sends a signal to the X-decoder circuit 11 for selecting WL. A decoder circuit (9) and an X-decoder circuit (11) for selecting WL; 제1항에 있어서, 상기 EQP발생회로(10)는 입력단(1)으로부터 신호를 받아 일정기간의 지연을 거쳐 일정한 폭을갖는 원 슛 퍼스(one shot pulse)를 생성시키는 것을 특징으로 하는 반도체 메모리의 전류감소회로.2. The semiconductor memory according to claim 1, wherein the EQP generating circuit 10 generates a one shot pulse having a predetermined width after receiving a signal from the input terminal 1 and passing a delay of a predetermined period. Current reduction circuit. 제2항에 있어서, 상기 일정기간의 지연은 워드라인 WL이 선택된후 판독동작이 완료되는 시점으로 선택되는 것을 특징으로 하는 반도체 메모리의 전류감소회로.3. The current reduction circuit of claim 2, wherein the delay of the predetermined period is selected as a time point at which the read operation is completed after the word line WL is selected. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910025749A 1991-12-31 1991-12-31 Current Reduction Circuit of Semiconductor Memory KR930014599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910025749A KR930014599A (en) 1991-12-31 1991-12-31 Current Reduction Circuit of Semiconductor Memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910025749A KR930014599A (en) 1991-12-31 1991-12-31 Current Reduction Circuit of Semiconductor Memory

Publications (1)

Publication Number Publication Date
KR930014599A true KR930014599A (en) 1993-07-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910025749A KR930014599A (en) 1991-12-31 1991-12-31 Current Reduction Circuit of Semiconductor Memory

Country Status (1)

Country Link
KR (1) KR930014599A (en)

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