KR100265604B1 - Word line driving apparatus for semiconductor memory - Google Patents

Abstract

PURPOSE: A device for driving a word line of a semiconductor memory device is provided to give a stabilization time of a bootstrap voltage in early operation of a semiconductor device and improve speed of a circuit by using an input signal of a bootstrap generator generating the bootstrap voltage activating a word line etc as an output signal of an RAS buffer. CONSTITUTION: The device for driving the word line includes an RAS buffer, a row address buffer, a row pre-decoder, a row decoder, a bootstrap generator(20) and a word line driver(40). The RAS buffer detects an external RAS and inverts into an internal RAS signal having a large driving force, and then supplies the inverted signal to an internal circuit of an RAS system being under the control of an RAS. The row address buffer exactly accepts an external address signal and inverts into a CMOS level of the inside of a memory. The row pre-decoder decodes an internal address generated from the address buffer. The row decoder is operated by a pre-decoded, thereby enabling a word line driving circuit. The bootstrap generator receives an output signal of the RAS buffer and generates a bootstrap voltage. The word line driver is driven by the bootstrap voltage, thereby activating a word line.

Description

Word line driver of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line driving device for a semiconductor memory device, and more particularly to a boost voltage generator for generating a boost signal for activating a word line or the like by a las signal.

In general, when NMOS is used as a cell transistor, the gate voltage is turned on only when the threshold voltage (Vt) is higher than the source voltage. However, since the maximum voltage applied to the DRAM is the power supply voltage (Vcc), the transferred voltage is the maximum value of Vcc-Vt. Only has a threshold voltage drop.

Therefore, in order to read or write the full voltage (Full Vcc) to the cell or the bit line, a voltage of Vcc + Vt or more must be applied to the cell transistor gate.

As a method of generating such a high voltage, a bootstrapping circuit method of generating a high voltage by pulse at the moment when the device starts operation by the ras signal / Ras is widely used.

The boost strap circuit generates a boost voltage only when the semiconductor device is selected and operates, and receives a predetermined signal as an input.

As shown in FIG. 1, the conventional boost generator 10 activates a word line through a system of output addresses → boost voltages → word lines of a loo predecoder. The timing of the address signal and the boost signal becomes very important, and if the timing is not correct, the memory device may not operate properly.

However, in the conventional boost strap circuit, it is difficult to precisely adjust the timing in the sequence, so that a time margin is added to this portion so that a reliable operation can be achieved. This causes a problem in optimizing the speed toward the low pass.

3A shows an operation timing thereof.

In the conventional boost generator 10, the boost strap voltage is generated using the output signal of the low predecoder, and thus the boost strap voltage cannot be sufficiently stabilized.

Therefore, the present invention was devised to solve such a conventional problem, and the boost signal is generated at the initial stage of operation of the semiconductor device by using the output signal of the las buffer as the input signal of the boost generator that generates the boost voltage for activating the word line. It is an object of the present invention to provide a word line driving device that gives a voltage stabilization time and improves the speed of a circuit.

1 is a block diagram of a boost device according to the prior art.

2 is a block diagram of a boost device according to an embodiment of the present invention.

3A is an operation timing diagram with respect to FIG.

3b is an operation timing diagram with respect to FIG.

* Explanation of symbols for main parts of the drawings

10, 20: boost trap generator 30, 40: word line drive device

Word line driving device of the present invention for achieving the above object is a boost generator for generating a boost voltage to the word line driver receives the output signal of the las buffer;

And a word line driver driven by the boost voltage to activate a word line.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic diagram of a word line driving apparatus according to an embodiment of the present invention, which detects an external lath and converts it into an internal lath signal having a large driving force, and then supplies the signal to an internal circuit of a lath system under lath control. Ras Buffer, Row Address Buffer to take external address signals accurately and convert them to CMOS levels in memory, and Row Predecoder to decode internal addresses generated from address buffers. A low decoder for operating a word line driver circuit by operating with a pre-decoded address signal and a output signal of the las buffer to generate a boost voltage through a word line driver. A bootstrap generator 20 and a word driven by the booststrap voltage to activate a wordline It consists of a driver (Word Line Driver) (40).

In the present invention, as shown in FIG. 3B, the boost trap generator is operated by using a las signal faster than the pre-decoded row address, so that there is sufficient time for activating the word line, and the circuit design can be optimized toward the low pass. It becomes the number. In FIG. 3B, the boost strap voltage is generated using the output signal of the las buffer to sufficiently stabilize the boost strap voltage.

As described above, by using the output signal of the las buffer to generate a boost voltage for activating a word line or the like, it is possible to give the boost voltage stabilization time as much as ▽ t and to optimize the circuit operating margin. have.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (2)

A lath buffer which detects an external lath and converts it into an internal lath signal having a large driving force, and then supplies the signal to an internal circuit of the lath system under ras control; A row address buffer that accurately receives an external address signal and converts it to a CMOS level in the memory; A row predecoder for decoding an internal address generated from the address buffer, A word line driving apparatus of a semiconductor memory device comprising a row decoder operating by a pre-decoded address signal to enable a word line driving circuit. A boost strap generator configured to receive an output signal of the lath buffer and generate a boost strap voltage; And a word line driver driven by the boost voltage to activate a word line. The method of claim 1, And the boost generator generates a boost voltage by receiving an output signal of a lath buffer.

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