KR100190758B1 - Word line driving circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line driving circuit of a semiconductor device, and more particularly, to a word line driving circuit capable of maintaining a high voltage on a word line while a lath signal is activated.

The word line driving circuit of the present invention includes a pull-up driver for applying a word line driving signal of a first voltage to an output terminal for driving an input line for inputting a word line driving signal from a low decoder and a selected word line. And a pull-down driver for applying a second voltage to an output terminal in a mode in which the word line is not operated, and a word line high voltage supplement circuit for supplying a high voltage to continuously maintain the word line.

Description

Word line driving circuit

1 is a word line driving circuit diagram of a conventional semiconductor device.

2 is a word line driver circuit diagram according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: input terminal 11: low decoder

12,22,201: inverter 20: word line high voltage supplementary circuit

N11, N21: EnMOS transistor for bootstrapping

N12, N22: NMOS transistor for pull-up

N13, N23: NMOS transistor for pull-down

P20: Switching PMOS transistor

The present invention relates to a word line driving circuit of a semiconductor device, and more particularly, to a word line driving circuit capable of maintaining a high voltage on a word line while a lath signal is activated.

Typically, the word line driver circuit is a large size buffer located at the end of a row decoder and takes the form of an NMOS type driver employing a double bootstrap method.

A conventional word line driver circuit will now be described with reference to FIG.

The conventional word line driving circuit shown in FIG. 1 has an input line 10 (n11) for inputting a word line driving signal from the row decoder 11 and a corresponding word line W10 for driving the selected word line. , A large pull-up NMOS transistor N12 for applying a high voltage word line driving signal (px +) to one of W11, W12, and W13), and is connected between a node n11 and a node n12. In the precharge mode in which the drive is controlled according to the application of the inverter 12 which inverts the word line driving signal from (11) and the output signal of the inverter 12 and the word line W13 is not operated, the word line ( W13) first bootstrapping a small pull-down NMOS transistor N13 for applying the ground voltage Vss and the word line driving signal input from the node n11 to a predetermined voltage (Vcc-Vt). ) And the word line drive of the voltage (Vcc-Vt) A bootstrapping NMOS transistor N11 is applied to control the operation of the pull-up NMOS transistor N12 by applying an arc to the gate terminal of the pull-up NMOS transistor N12.

First, if a set of row decoders 11 is selected because a ras signal (called RAS, hereinafter referred to as RAS) is activated, and a row address is pre-decoded, a high level word line driving signal is transmitted through the input line 10 to the node n11. Is applied to the NMOS transistor N11 and the inverter 12 for bootstrapping.

Accordingly, when the voltage of the first bootstrap node NB11 increases due to the voltage of the node n11 and reaches Vcc-Vt (Vcc: power supply voltage, Vt: threshold voltage of the NMOS transistor N11), the NMOS transistor N11 ) Is turned off and the first bootstrap node NB11 is isolated with a voltage of Vcc-Vt. At the same time, the high level is inverted to the low level through the second node N12 through the inverter 11 and the pull-down NMOS transistor N13 is turned off.

After that, after a predetermined time, the bootstrapping voltage Vpp is applied to the pull-up NMOS transistor N12.

Accordingly, the first bootstrap node NB11, which maintains a potential lower than the threshold voltage Vt of the pull-up NMOS transistor N12 than the power supply voltage Vcc, has a high voltage Vcc-Vt higher than the power supply voltage Vcc. + Vpp), and a high voltage is transmitted to the word line W13 through the pull-up NMOS transistor N12 by the boosted voltage. That is, the voltage of the first bootstrap node NB11 rises due to the junction capacitance between the nodes px +, and its potential is about Vcc-Vt + Vpp, which is the threshold voltage of the pull-up NMOS transistor N12. The gate voltage is large enough to compensate for the (Vt) loss.

The above technique relates to a double bootstrap type word line driving circuit having a multi-stage decoder among techniques currently used in dynamic RAM.

If the Rasbah signal (Row Address Strobe, RAS / RAS) is active and maintains its state for a very long time, it is often the case that the DRAM is applied in various page modes.

Even if you are not in page mode, if the system requires an operation that requires intermittent activation of a column address strobe (or CAS) after one activation of the rasbar, the request must be accepted. In other words, in the technical aspect of the method for maintaining a very long / RAS enabled state, when / RAS is activated, the address signal is simultaneously received and the pre-decoded signal reaches the ROH decoder 11 There is a method of bootstrapping the first bootstrap node NB11 and activating the wordline driving signal px + by multi-step decoding. That is, as described above, the first bootstrap node NB11 may maintain a high bootstrap-high voltage of about Vcc-Vt + Vpp to ensure the level of the activated word line.

However, the level of the first bootstrap node NB11 continues to fall due to the leakage current below the threshold voltage Vt of the NMOS transistor N11 for bootstrapping and the junction leakage current at the first bootstrap node NB11. do.

If the voltage drops to the level of Vcc-Vt, the pull-up NMOS transistor N12 cannot continuously supply a high voltage to the word line W13 and the word line W13 enters a floating state. From then on, the word line is unprotected from various noises.

This problem also occurs when entering the las precharge. That is, when / RAS completes the cycle and enters the precharge state, the word line driving signal px + first transitions to the ground and the first bootstrap node NB11 must maintain the current level during the transition. In other words, if the level is not kept by the leakage current during the long / RAS activation period, this operation can not be guaranteed.

In order to prevent the above phenomenon, in terms of device technology, a low threshold voltage may be specially devised for the device of the portion or a doping technique may be applied to reduce junction leakage. Will be advantageous.

Accordingly, an object of the present invention is to provide a word line driving circuit having a stable activation state capable of maintaining a high voltage on a word line while a ras signal is activated.

In order to achieve the above object, a word line driving circuit according to an embodiment of the present invention includes an input line for inputting a word line driving signal from a row decoder;

A pull-up driver for applying a first voltage to a selected word line by the word line driving signal;

A pull-down driver applying a second voltage to the word line in the deactive mode of the word line;

And a word line high voltage supplementary circuit for supplying a high voltage to keep the word line continuously active.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a word line driver circuit diagram according to an embodiment of the present invention.

In FIG. 2, the word line driver circuit of the present invention includes an input line 10 for inputting a word line driver signal and a first voltage Vcc-Vt + Vpp at an output terminal for driving a selected word line WL. A pull-up NMOS transistor N22 for applying a word line driving signal of the ") and a pull-down NMOS transistor for applying a second voltage Vss to an output terminal in a mode in which the word line WL is not operated. And a word line high voltage supplemental circuit 20 for supplying a high voltage in order to keep the word line WL continuously active.

The word line high voltage supplemental circuit 20 is connected to the word line WL and the switching PMOS transistor P20 for switching the supply of the high voltage transferred to the word line WL, and the switching PMOS An inverter 201 connected to the transistor P20 and controlling the switching of the switching PMOS transistor P20 is provided.

The operation of the present invention configured as described above will be described below.

Inverter of the word line high voltage supplemental circuit 20 when the word line WL transitions to the high level state of the high voltage Vcc-Vt + Vpp by activation of the las signal by the operation of the word line driving circuit of the present invention described above. According to the control of 201, that is, the word line WL is high level, and is inverted to a low level control signal through the inverter 201.

The inverted low level signal is then applied to the gate terminal of the switching PMOS transistor P20.

As a result, the switching PMOS transistor P20 is turned on.

Accordingly, the word line activation high voltage Vpp supplied from the means for supplying a voltage higher than the power supply voltage is transferred to the word line WL through the word line switching PMOS transistor P20. That is, it is continuously supplied to the word line WL to maintain a stable activation state. That is, even if the word line WL is floated because the las active state becomes long and the bootstrap node NB11 cannot maintain a level of about Vcc-Vt + Vpp, the word line WL remains the word line high voltage supplement circuit 20. Since the high voltage level is maintained by the high voltage supplied from, the noise level is maintained even when the word line WL is in the standby state.

After that, when the signal from the row decoder 11 enters the standby state, a low level signal is input to the inverter 22. The low level signal is inverted to high level in the inverter 22 and applied to the gate of the pull-down NMOS transistor N23.

Accordingly, the pull-down NMOS transistor N23 is turned on to maintain the word line WL at the battery voltage Vss state, and the bootstrap node NB11 is also brought into the deactivated state before the NMOS transistor N22 is turned on. Becomes standby.

In this process, since the pull-up NMOS transistor N22 is designed to be much larger than the PMOS transistor P20 of the word line high voltage supplemental circuit 20, the pull-up NMOS transistor N22 does not interfere with the transition of the pull-up NMOS transistor N22. Since the pull-down NMOS transistor N23 is designed to be much larger than the PMOS transistor P20, the standby state of the word line WL remains stable against noise.

According to the present invention as described above, the word line driving circuit of the semiconductor device of the present invention has the effect of ensuring the stability to the long lath activation state.

Claims (4)

An input line for inputting a word line driving signal from the row decoder; A pull-up driver for applying a first voltage to the selected word line by the word line driving signal; A pull-down driver applying a second voltage to the word line in the deactive mode of the word line; And a word line high voltage supplementary circuit for supplying a high voltage to keep the word line continuously active. The method of claim 1, The word line high voltage supplement circuit includes switching means for switching a supply of a high voltage connected to the word line and delivered to the word line; And a control means connected to said switching means for controlling switching of the switching means. The method of claim 2, And said switching means is a PMOS transistor. The method of claim 2, And said control means is an inverter.