KR930012338U - D플립플롭 논리회로 - Google Patents
D플립플롭 논리회로Info
- Publication number
- KR930012338U KR930012338U KR2019910019460U KR910019460U KR930012338U KR 930012338 U KR930012338 U KR 930012338U KR 2019910019460 U KR2019910019460 U KR 2019910019460U KR 910019460 U KR910019460 U KR 910019460U KR 930012338 U KR930012338 U KR 930012338U
- Authority
- KR
- South Korea
- Prior art keywords
- flip
- logic circuit
- flop logic
- flop
- circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910019460U KR940004024Y1 (ko) | 1991-11-14 | 1991-11-14 | D플립플롭 논리회로 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910019460U KR940004024Y1 (ko) | 1991-11-14 | 1991-11-14 | D플립플롭 논리회로 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930012338U true KR930012338U (ko) | 1993-06-25 |
| KR940004024Y1 KR940004024Y1 (ko) | 1994-06-17 |
Family
ID=19322210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019910019460U KR940004024Y1 (ko) | 1991-11-14 | 1991-11-14 | D플립플롭 논리회로 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940004024Y1 (ko) |
-
1991
- 1991-11-14 KR KR2019910019460U patent/KR940004024Y1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940004024Y1 (ko) | 1994-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE69024431D1 (de) | Flipflop-Schaltung | |
| DE69225537D1 (de) | Integrierte Speicherschaltung | |
| KR900011154A (ko) | 논리레벨 변환회로 | |
| DE4291224T1 (de) | BiCMOS-Logik-Verknüpfungsschaltung | |
| DE69206651D1 (de) | Schaltungsanordnung | |
| DE69213986D1 (de) | Schaltungsanordnung | |
| DE68926518T2 (de) | Flipflop-Schaltung | |
| DE69132540D1 (de) | Programmierbare logische Schaltung | |
| DE69306131D1 (de) | Komplementäre logische Schaltung | |
| DE69128500D1 (de) | Emittergekoppelte logische Schaltung | |
| DE69128439T2 (de) | Flip-Flop-Schaltung | |
| DE69123100D1 (de) | CMOS-Flipflop-Schaltung | |
| DE69126832D1 (de) | BiCMOS logische Schaltung | |
| DE69123167D1 (de) | Bi-MOS-integrierte logische Schaltung | |
| DE68916249D1 (de) | Logikschaltung. | |
| KR900010777A (ko) | 고속 국부 억세스 시간을 갖는 집적회로 구성물 | |
| DE69122184T2 (de) | Schwellenfreie logische Schaltung | |
| DE69221455T2 (de) | Zentrierschaltung | |
| KR930012338U (ko) | D플립플롭 논리회로 | |
| DE69223660D1 (de) | Fehlersichere Logikschaltung | |
| KR930012326U (ko) | 씨모스 논리회로 | |
| KR890017883A (ko) | 논리회로 | |
| DE59009022D1 (de) | Integrierte Flip-Flop-Schaltung. | |
| KR880006849A (ko) | 논리회로 | |
| KR930012331U (ko) | 다용도 플립플롭 회로 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| REGI | Registration of establishment | ||
| FPAY | Annual fee payment |
Payment date: 20050524 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |