KR930010671B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR930010671B1
KR930010671B1 KR1019880010247A KR880010247A KR930010671B1 KR 930010671 B1 KR930010671 B1 KR 930010671B1 KR 1019880010247 A KR1019880010247 A KR 1019880010247A KR 880010247 A KR880010247 A KR 880010247A KR 930010671 B1 KR930010671 B1 KR 930010671B1
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polycrystalline silicon
impurity implantation
film
type
semiconductor device
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KR1019880010247A
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Korean (ko)
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KR900003975A (en
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이철진
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삼성전자 주식회사
김광호
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The semiconductor device is mfd. by (a) forming a N-type well (2), and N- and P- impurity implanting region (3,4) on the semiconductor device, (b) forming an insulating film and a contact hole (8), (c) depositing a polycrystalline silicon (6), (d) covering a photoresist (9) on the whole surface of the silicon (6), etching-back it, (e) implanting a P-type and a N-type impurity into the respective regions (3,4), (f) covering a metal wiring film (7) on the regions (3,4), and connecting the regions (3,4) with each other. The method lowers a contact resistance in the impurity implanting region, and increases a step coverage of the metal wiring film in the contact hole.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

제1도는 종래의 방법으로 불순물 주입영역을 연결한 배선막을 나타낸 도면.1 is a view showing a wiring film connecting impurity implantation regions by a conventional method.

제2도는 콘택홀에서의 금속막의 스텝커버리지를 나타낸 도면.2 is a diagram showing step coverage of a metal film in a contact hole.

제3도는 본 발명의 반도체 장치의 제조공정도.3 is a manufacturing process diagram of a semiconductor device of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : P형 기판 2 : N형 웰1: P type substrate 2: N type well

3 : N-불순물 주입영역 4 : P-불순물 주입영역3: N - impurity implantation region 4: P - impurity implantation region

5 : 절연막 6 : 다결정 실리콘5: insulating film 6: polycrystalline silicon

7 : 금속배선막 8 : 콘택홀7: metal wiring film 8: contact hole

9-11 : 포토레지스트9-11: Photoresist

본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 N-불순물 주입영역과 P-불순물 주입영역에서 콘택저항을 낮추면서 금속배선막의 콘택 스텝 커버리지를 증가시킬 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for increasing contact step coverage of a metal wiring film while reducing contact resistance in an N - impurity implantation region and a P - impurity implantation region.

반도체 장치의 제조공정중 금속배선막을 연결시킬 때 N-불순물 주입영역과 P-불순물 주입영역을 동시에 연결시키는 배선 기술이 고집적 반도체 소자에서 요구되고 있다.There is a need for a highly integrated semiconductor device in which a wiring technique of simultaneously connecting an N - impurity implantation region and a P - impurity implantation region when connecting a metal interconnection film during a manufacturing process of a semiconductor device.

N-불순물 주입영역과 P-불순물 주입영역을 동시에 연결시킬 때 금속배선막과 불순물 주입영역 사이의 오믹 콘택의 형성이 어려운 문제점이 있었다.When the N - impurity implantation region and the P - impurity implantation region are simultaneously connected, it is difficult to form an ohmic contact between the metal wiring layer and the impurity implantation region.

즉, 배선저항을 낮추고 콘택 저항을 감소시키기 위해 배선막에 N-또는 P-형 불순물을 주입시키는 경우 배선막과 불순물 주입영역의 불순물의 종류가 서로 다른 콘택에서 다이오드가 형성되어 콘택저항이 매우 높아지게 된다.That is, when N - or P - type impurities are injected into the wiring film in order to lower the wiring resistance and reduce the contact resistance, diodes are formed in the contacts having different types of impurities in the wiring film and the impurity implantation region so that the contact resistance becomes very high. do.

제1도는 종래의 방법으로 불순물 주입영역을 연결하는 배선방법으로서, 배선막의 종류를 이층막 구조로 하였다.1 is a wiring method for connecting impurity implantation regions by a conventional method, and the type of wiring film has a two-layer film structure.

제1배선막으로 N-형 불순물이 도우핑된 다결정 실리콘(6)과 제2배선막으로 금속막(7)을 사용하였다.Polycrystalline silicon 6 doped with N − type impurities as the first wiring film and a metal film 7 as the second wiring film were used.

배선막으로 사용된 N-형 불순물이 도우핑된 다결정 실리콘(6)과 P-불순물 주입영역(4) 사이에 상기 설명한 바와 같이 다이오드가 형성되어 콘택저항이 증가하게 되는 문제점이 있었다.As described above, a diode is formed between the polycrystalline silicon 6 doped with the N − type impurity used as the wiring film and the P − impurity implantation region 4 to increase the contact resistance.

또한, 고집적반도체 소자에서 콘택홀의 크기가 매우 줄어들게 되므로 제2도에 도시된 것처럼 금속배선막의 스텝커버리지가 나빠지기 때문에 배선저항이 증가하는 문제점이 있었다.In addition, since the size of the contact hole in the highly integrated semiconductor device is greatly reduced, as shown in FIG.

본 발명은 N-불순물 주입영역과 P-불순물 주입영역을 금속배선막을 사용하여 동시에 연결할 때 N-불순물 주입영역과 P-불순물 주입영역에 같은 종류의 불순물을 다결정 실리콘에 주입시키므로써 각각의 콘택에서 안정된 오믹 콘택을 형성시켜 콘택저항을 낮출 수 있는 반도체장치의 제조방법을 제공함에 그 목적이 있다.In the present invention, when the N - impurity implantation region and the P - impurity implantation region are simultaneously connected by using a metal interconnection film, the same type of impurity is injected into the polycrystalline silicon in the N - impurity implantation region and the P - impurity implantation region at each contact. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a stable ohmic contact to lower the contact resistance.

본 발명의 다른 목적은 콘택홀에서 금속배선막의 스텝커버리지를 증가시켜 배선저항을 감소시킬 수 있는 반도체장치의 제조방법을 제공함에 그 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing wiring resistance by increasing step coverage of a metal wiring film in a contact hole.

본 발명의 반도체장치의 제조방법 P형 반도체 기판에 N형 불순물을 이온 주입한 다음 확산시켜 N형 웰을 형성하고, 실리콘기판에 N-형 및 N웰내에 P-형 불순물을 이온 주입시켜 N-불순물 주입영역과 P-불순물 주입영역을 만들며, 절연막을 도포시켜 N-불순물 주입영역과 P-불순물 주입영역에 각각 콘택홀을 형성하고, 다결정 실리콘을 도포시킨 다음 에치백을 실시하여 콘택홀 부분에만 다결정 실리콘을 남겨놓으며, 콘택홀에 남아있는다결정 실리콘에 N-불순물 주입영역과 P-불순물 주입영역과 같은 종류의 불순물을 이온주입 시킨 다음 열처리를 실시하여 오믹콘택을 형성하고, 금속배선막을 도포시키는 것이다.And forming an N-type ion-implanted and then diffused to N-type well impurity to the production method P-type semiconductor substrate of the semiconductor device of the present invention, N in the silicon substrate by ion implantation to form an impurity N-P in the type and N well- An impurity implantation region and a P - impurity implantation region are formed, and an insulating film is applied to form contact holes in the N - impurity implantation region and the P - impurity implantation region, respectively, polycrystalline silicon is applied, and then etched back to the contact hole portion only. Leave polycrystalline silicon and ion-implant the same kind of impurities as N - impurity implantation region and P - impurity implantation region and then heat treatment to form ohmic contact and apply metal wiring film will be.

이하에 첨부된 도면에 의거하여 본 발명의 실시예를 상세히 설명한다.Exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제3도는 본 발명의 실시예에 다른 반도체장치의 제조공정도를 나타낸 것이다.3 is a manufacturing process diagram of a semiconductor device according to the embodiment of the present invention.

P형 실리콘기판(1)에 N형 불순물을 이온주입한 다음 확산시켜 N형 웰(2)을 형성하고 P형 실리콘기판(1)과 N형 웰(2)내에 각각 N-및 P-형 불순물을 이온주입시켜 N-불순물 주입영역(3)과 P-불순물 주입영역(4)을 형성한 다음 그 위에 절연막(5)을 도포시키면 제3a도와 같다.Ion-implanting N-type impurity in the P-type silicon substrate 1 form the next spread by the N-type well (2), each in a P-type silicon substrate 1 and the N-type well (2) N -, P - type impurity Ion implantation to form the N - impurity implantation region 3 and the P - impurity implantation region 4 and then apply the insulating film 5 thereon, as shown in FIG. 3A.

절연막(5)을 도포시킨 다음 N-및 P-불순물 주입영역(3,4)의 절연막(5)을 식각하여 콘택홀(8)을 형성하면 제3b도와 같다. 콘택홀을 형성한 다음 제3c도와 같이 다결정 실리콘(6)을 도포시키고, 다결정 실리콘(6) 위에 포토레지스트(9)를 제3d도와 같이 도포시킨 후 건식식각 장치에서 식각 선택비를 조절하여 다결정 실리콘(6)의 에치백을 실시하면 제3e도처럼 콘택홀에만 다결정 실리콘(6)이 존재하고 그 이외의 다결정 실리콘은 제거된다.After the insulating film 5 is applied, the insulating film 5 of the N − and P − impurity implantation regions 3 and 4 is etched to form the contact hole 8, as shown in FIG. 3B. After forming the contact hole, the polycrystalline silicon 6 is coated as shown in FIG. 3c, the photoresist 9 is coated on the polycrystalline silicon 6 as shown in FIG. 3d, and then the etch selectivity is adjusted in the dry etching apparatus. When the etch back of (6) is performed, as shown in FIG. 3E, the polycrystalline silicon 6 exists only in the contact hole, and other polycrystalline silicon is removed.

다시 포토레지시트(10)를 도포한 다음 포토레지스트 패턴을 형성하여, N-불순물 주입영역(3)의 콘택홀을 형성한 다음 N-형 불순물을 다결정 실리콘(6)에 주입시키고 포토레지스트(10)를 제거한다. 포토레지스터(11)를 도포시키고 포토레지스트 패턴을 형성하여 P-불순물 주입영역(4)의 콘택홀을 연 다음 다결정 실리콘(6)에 제3g도 처럼 P-형 불순물을 주입시킨다.After applying the photoresist sheet 10 again, a photoresist pattern is formed to form a contact hole in the N − impurity implantation region 3. Then, the N − type impurity is implanted into the polycrystalline silicon 6 and the photoresist 10 is formed. ). The photoresist 11 is applied and a photoresist pattern is formed to open the contact hole of the P − impurity implantation region 4, and then the P − type impurity is implanted into the polycrystalline silicon 6 as shown in FIG. 3g.

포토레지스트(11)을 제거한 다음 900℃에서 30분동안 확산로에서 열처리를 실시하여 다결정 실리콘(6)과 N-및 P-불순물 주입영역(3,4) 사이에 오믹콘택을 형성시키고, 금속배선막(7)을 도포시켜 N-및 P-불순물 주입영역(3,4)을 제3h도 처럼 연결시킨다.After the photoresist 11 is removed, heat treatment is performed in a diffusion furnace at 900 ° C. for 30 minutes to form an ohmic contact between the polycrystalline silicon 6 and the N − and P − impurity implantation regions 3 and 4, and the metal wiring The film 7 is applied to connect the N - and P - impurity implantation regions 3 and 4 as shown in FIG. 3h.

금속배선막으로 실리사이드막, 내열성(Refractory) 금속막 또는 알루미늄 합금막을 사용하고, 금속배선막 대신 불순물을 주입시킨 다결정 실리콘을 사용할 수도 있다.As the metal wiring film, a silicide film, a refractory metal film, or an aluminum alloy film may be used, and polycrystalline silicon into which impurities are injected may be used instead of the metal wiring film.

본 발명은 N-및 P-불순물 주입영역을 금속배선막을 사용하여 동시에 연결할 때 N-및 P-콘택홀에 다결정 실리콘을 채워넣고 같은 종류의 불순물을 주입시킨 후 금속배선막을 도포시키므로서 다결정 실리콘과 N-및 P-불순물 주입영역 사이에 안정된 오믹콘택을 형성시켜 콘택저항을 낮출 수 있으며, 또한 콘택홀에서 금속배선막의 스텝커버리지를 증가시켜 배선저항을 감소시킬 수 있다.When the N - and P - impurity implantation regions are simultaneously connected using a metal interconnection film, the present invention fills polycrystalline silicon into the N - and P - contact holes, injects the same kind of impurity, and then applies a metal interconnection film. A stable ohmic contact can be formed between the N - and P - impurity implantation regions to reduce the contact resistance, and the wiring resistance can be reduced by increasing the step coverage of the metal wiring film in the contact hole.

Claims (4)

N-불순물 주입영역과 P-불순물 주입영역 간을 금속배선막으로 연결하는 반도체 장치의 제조방법에 있어서, 반도체 기판(1) 상에 N형 웰(2), N-불순물 주입영역(3) 및 P-불순물 주입영역(4)을 형성하는 제1단계와, 상기 제1단계의 결과적 구조 위에 절연막을 형성하고 사진식각방법으로 상기 N-및 P-불순물 주입영역(3)(4)에 대응되는 위치에 배선연결를 위한 콘택홀(8)을 형성하는 제2단계와, 상기 제2단계의 결과적 구조 위에 다결정 실리콘(6)을 증착하는 제3단계와, 상기 다결정 실리콘(6)의 전면에 포토레지스트(9)를 도포하고 에치백하여 상기 콘택홀(8)내에 다결정 실리콘이 남게 하고 그외 부분의 다결정 실리콘은 제거하는 제4단계와, 상기 콘택홀(8)내에 남은 다결정 실리콘(6)중에서 P-불순물 주입영역 위에 대해서는 P형 불순물을 주입하고 N-형 불순물 주입영역 위에 대해서는 N형 불순물을 주입하는 제5단계와, 상기 제5단계의 결과적 구조 위에 금속배선막(7)을 도포하여 상기 N-불순물 주입영역(3)과 P-불순물 주입영역(4)를 연결하는 제6단계로 이루어지는 것을 특징으로 하는 반도체 장치의 제조방법.A semiconductor device manufacturing method for connecting a N - impurity implantation region and a P - impurity implantation region with a metal wiring film, comprising: an N-type well 2, an N - impurity implantation region 3, and a semiconductor substrate 1; A first step of forming the P − impurity implantation region 4 and an insulating film formed on the resultant structure of the first step and corresponding to the N − and P − impurity implantation regions 3 and 4 by a photolithography method A second step of forming a contact hole 8 for wiring connection at a position; a third step of depositing polycrystalline silicon 6 on the resulting structure of the second step; and a photoresist on the entire surface of the polycrystalline silicon 6; (9) applying and etching back to leave the polycrystalline silicon in the contact hole (8) and to remove the polycrystalline silicon in the other portion, and P - of the remaining polycrystalline silicon (6) in the contact hole (8) implanting P-type impurity for impurity implantation region over the N - type fire For on the water injection area, and fifth step for implanting N-type impurities, by coating a metal wiring film (7) on the result the structure of the fifth step the N - doping region 3 and the P - doping region (4 And a sixth step of connecting the same). 제1항에 있어서, 금속배선막(7)은 실리사이드막, 내열성 금속막 또는 알루미늄합금 중 그 어느 하나로 형성되는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the metal wiring film (7) is formed of any one of a silicide film, a heat resistant metal film or an aluminum alloy. 제1항에 있어서, 금속배선막(7)은 불순물을 주입한 다결정 실리콘 막으로 형성되는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the metallization film (7) is formed of a polycrystalline silicon film into which impurities are implanted. 제1항에 있어서, 제5단계의 불순물 주입공정은 다결정 실리콘(6) 위에 포토레지스터(11)를 노광 현상하는 사진공정으로 패턴을 형성하여 다결정 실리콘(6)에 N형 및 P형 불순물을 주입하는 것을 특징으로 하는 반도체 장치의 제조방법.The impurity implantation process of claim 5 is a photolithography process of exposing and developing the photoresist 11 on the polycrystalline silicon 6 to form a pattern to inject N-type and P-type impurities into the polycrystalline silicon 6. The manufacturing method of a semiconductor device characterized by the above-mentioned.
KR1019880010247A 1988-08-11 1988-08-11 Manufacturing method of semiconductor device KR930010671B1 (en)

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