KR920000704B1 - Metallic wire film manufacturing method of semiconductor device - Google Patents

Metallic wire film manufacturing method of semiconductor device Download PDF

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KR920000704B1
KR920000704B1 KR1019880009642A KR880009642A KR920000704B1 KR 920000704 B1 KR920000704 B1 KR 920000704B1 KR 1019880009642 A KR1019880009642 A KR 1019880009642A KR 880009642 A KR880009642 A KR 880009642A KR 920000704 B1 KR920000704 B1 KR 920000704B1
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film
impurity
polycrystalline silicon
semiconductor device
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KR900002410A (en
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김일권
김원철
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삼성전자 주식회사
김광호
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

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Abstract

Metal wiring film is stepoisely manufctured by (1) preparing a wafer in which n+ type inpurity region is formed on p type silicon substrate and p+ type impurity region is formed in n type well, (2) coating silicon to connect two high conc.inpurity regions through contact hole, (3) coating high m.p.metal film on the polycrystalline silicon layer, and (4) forming silicide film by heat-treating the high m.p. metal film at high temperature, while diffusing impurities into polycrystalline silicon near high conc. inpurity regions. Additionally inpurities are injected by image reversal to reduce contact resistance between high conc. inpurity regions and polycrystalline silicon.

Description

반도체 장치의 금속배선막 제조방법Method for manufacturing metal wiring film of semiconductor device

제1a도와 (b)는 종래의 금속배선막을 갖는 반도체 장치의 단면도.1A and (B) are cross-sectional views of a semiconductor device having a conventional metal wiring film.

제2도는 본 발명 금속배선막 제조방법의 일실시예에 따른 반도체 장치의 단면도.2 is a cross-sectional view of a semiconductor device according to an embodiment of the method for manufacturing a metal wiring film of the present invention.

제3도는 본 발명 금속배선막 제조방법의 다른 실시예에 따른 반도체 장치의 단면도.3 is a cross-sectional view of a semiconductor device according to another embodiment of the method for manufacturing a metal wiring film of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

3 : N+불순물 주입영역 4 : P+불순물 주입영역3: N + impurity implantation zone 4: P + impurity implantation zone

6 : 다결정 실리콘 7 : 고융점 금속막6: polycrystalline silicon 7: high melting point metal film

10 : N형 불순물이 도핑된 다결정 실리콘10: polycrystalline silicon doped with N-type impurities

11 : P형 불순물이 도핑된 다결정 실리콘11: polycrystalline silicon doped with P-type impurities

본 발명은 반도체 장치에 있어서 고농도 전자 불순물과 고정도 정공불순물(이하 각각 N+와 P+불순물이라 칭함) 주입영역을 동시에 연결하는 금속배선막을 갖는 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a semiconductor device having a metal wiring film which simultaneously connects a high concentration electron impurity and a highly precise hole impurity (hereinafter referred to as N + and P + impurities) injection regions in a semiconductor device.

반도체 장치에 있어서 N+불순물 주입영역과 P+불순물 주입영역을 동시에 연결시키는 배선 기술을 배선막과 불순물 주입영역 사이의 접촉저항이 커지는 문제점이 발생된다.In the semiconductor device, a problem arises in that a wiring technique for connecting the N + impurity implantation region and the P + impurity implantation region at the same time increases the contact resistance between the wiring film and the impurity implantation region.

즉 배선 저항을 낮추고 접촉저항을 감소시키기 위하여 배선막에 N형 또는 P형 불순물을 주입하게 되면 배선막과 불순물 주입영역의 불순물 종류가 서로 다른 어느 한쪽의 접촉 부분에서는 다이오드가 형성되어 접촉저항이 매우 높아지게 된다.In other words, when N-type or P-type impurities are injected into the wiring film in order to lower the wiring resistance and reduce the contact resistance, a diode is formed at one of the contact portions having different impurity types between the wiring film and the impurity implantation region, resulting in very high contact resistance. Will be higher.

제1a도는 이러한 종래의 반도체 장치의 일예를 도시한 것으로, N+불순물 주입영역(3)과 P+불순물 주입영역(4)을 연결하기 위하여 고융점 금속막(7)을 N+불순물로 도핑된 다결정 실리콘(6)과 함께 2중막으로 구성하면, 상기 다결정 실리콘(6)과 P+불순물 주입영역(4)이 다이오드로서 동작하기 때문에 접촉저항이 매우 높아지게 된다.FIG. 1A illustrates an example of such a conventional semiconductor device, in which the high melting point metal film 7 is doped with N + impurities to connect the N + impurity implantation region 3 and the P + impurity implantation region 4. When the double film is formed together with the polycrystalline silicon 6, the contact resistance becomes very high because the polycrystalline silicon 6 and the P + impurity implantation region 4 operate as a diode.

따라서 제1b도는 상기 제1a도의 단점을 보완하기 위하여 사용되어지던 종래의 반도체 장치로서, N+불순물 주입영역(3)과 P+불순물 주입영역(4)을 직접 접촉시키지 않고 P+불순물 주입영역에는 추가된 별도의 금속막(9)에 의하여 금속막(7)과 접촉시키므로써 서로 다른 불순물 영역의 접합에 의한 접촉저항을 줄여주도록 한다. 그러나 상기한 제1b도의 반도체 장치는 금속막(9)을 구성하기 위한 공정이 중복되어지므로 반도체 장치의 설계 및 공정이 복잡해지는 단점이 있었다.Accordingly, FIG. 1B is a conventional semiconductor device that has been used to compensate for the disadvantages of FIG. 1A. In FIG. 1B, the P + impurity implantation region is not directly contacted with the N + impurity implantation region 3 and the P + impurity implantation region 4. The additional metal film 9 makes contact with the metal film 7 to reduce contact resistance due to the joining of different impurity regions. However, the semiconductor device of FIG. 1B has a disadvantage in that the design and the process of the semiconductor device are complicated because the processes for forming the metal film 9 are overlapped.

본 발명은 이와같은 종래의 문제점을 개선하기 위하여 개발된 것으로, 본 발명의 목적은 반도체 장치의 제조공정에서 N+불순물 주입영역과 P+불순물 주입영역을 금속배선막을 사용하여 동시에 연결시킬 때 각각의 불순물 주입영역에서의 접촉저항을 낮추고, 이와 함께 금속배선막의 저항을 낮추는 방법을 제공하는데 있다.The present invention was developed to improve such a conventional problem, and an object of the present invention is to provide a method of connecting the N + impurity implantation region and the P + impurity implantation region at the same time by using a metal interconnection film in the manufacturing process of a semiconductor device. The present invention provides a method of lowering the contact resistance in the impurity implantation region and simultaneously reducing the resistance of the metal wiring film.

상기한 목적을 달성하기 위하여 본 발명에서는 금속배선막이 N+확산영역 및 P+확산영역과 접하는 부분에서는 확산영역과 같은 타입의 불순물을 함유하도록 구성한다.In order to achieve the above object, in the present invention, the metal wiring film is configured to contain an impurity of the same type as the diffusion region in the portion in contact with the N + diffusion region and the P + diffusion region.

이와 첨부된 제2도의 본 발명 반도체 장치의 공정 단면도를 참조하여 본 발명을 상세히 설명한다.The present invention will be described in detail with reference to the process sectional view of the semiconductor device of the present invention shown in FIG.

P형 반도체 기판(1)위에 N형 웰(well)(2)을 형성한 후 N+불순물 주입영역(3)과 P+불순물 주입영역(4)을 만들고 나서 절연막(5)을 도포한다.After forming an N-type well 2 on the P-type semiconductor substrate 1, an N + impurity implantation region 3 and a P + impurity implantation region 4 are formed, and then an insulating film 5 is applied.

그 다음 도포시킨 절연막(5)을 식각하여 접촉홀을 형성한 후 다결정 실리콘 막(6)과 고융점 금속막(7)을 도포시킨다.Then, the coated insulating film 5 is etched to form contact holes, and then the polycrystalline silicon film 6 and the high melting point metal film 7 are coated.

이때 다결정 실리콘막(6)은 종래와는 달리 불순물이 도핑되지 않는 것을 사용한다. 여기까지의 공정이 제2a-d도까지 도시된 것이며 제2e도는 상기한 제2d도의 공정후에 고온 열처리를 수행하여 고융점 금속막(7)과 다결정 실리콘(6)이 반응하여 실리사이드막(12)을 형성함과 동시에 N+불순물 주입영역(3)과 P+불순물 주입영역(4)의 불순물이 다결정 실리콘(6) 방향으로 확산하여 접합부위에 불순물이 도핑된 다결정 실리콘(10,11)을 형성한 것을 도시한 것이다. 따라서 다결정 실리콘(10)은 N형 불순물이 도핑되어 있고 다결정 실리콘(11)은 P형 불순물이 도핑되어, 접촉되어 있는 고농도의 불순물 확산영역(3,4)과 모두 같은 형의 불순물을 갖게 된다.At this time, unlike the conventional art, the polycrystalline silicon film 6 is one in which impurities are not doped. The process up to this point is shown to FIGS. 2a-d, and FIG. 2e shows the high melting point metal film 7 and the polycrystalline silicon 6 to react with the silicide film 12 after performing the high temperature heat treatment after the process of FIG. At the same time, impurities in the N + impurity implantation region 3 and the P + impurity implantation region 4 diffuse in the direction of the polycrystalline silicon 6 to form polycrystalline silicon 10 and 11 doped with impurities at the junction. It is shown. Therefore, the polycrystalline silicon 10 is doped with N-type impurities, and the polycrystalline silicon 11 is doped with P-type impurities, so that all of the high-concentration impurity diffusion regions 3 and 4 that are in contact have impurities of the same type.

제3도는 본 발명의 다른 실시예를 도시한 것으로 고융점 금속막(7)을 도포하기 전인 제2c도의 공정을 완료하고나서 접촉저항의 개선을 목적으로 불순물을 다결정 실리콘(6)에 도핑할 경우를 도시한 것이다.FIG. 3 shows another embodiment of the present invention, in which the doping of the polycrystalline silicon 6 with impurities for the purpose of improving the contact resistance after completing the process of FIG. 2c before the high melting point metal film 7 is applied. It is shown.

제3a도는 사진공정과 이온 주입공정을 이용하여 N+불순물 주입영역(3)과의 접촉부위를 N형 불순물로 도핑하는 것을 나타낸 것이고, 제3b도는 사진공정을 한번 더하여 P+불순물 주입영역(4)과의 접촉부위를 P형 불순물로 도핑하는 것을 나타낸 것이다. 이후 포토레지스트(13)를 제거하고 제2d도와 (e) 공정을 수행하여 자항성접촉(Ohmic contact)을 형성한다.FIG. 3a shows the doping of the contact region with the N + impurity implantation region 3 with N type impurity using the photolithography process and the ion implantation process. FIG. 3b shows the P + impurity implantation region 4 with the addition of the photolithography process. ) Shows doping with P-type impurities. Thereafter, the photoresist 13 is removed and the second contact diagram (e) is performed to form an ohmic contact.

한편 상기 제3도의 공정에서 불순물을 다결정 실리콘으로 주입할 때에는 역상(image reversal)법을 이용한 사진공정으로서 불순물을 주입할 수 있으며, 또한 한 종류의 불순물을 사진공정없이 다결정 실리콘으로 전면에 주입하고 다른 종류의 불순물을 사진공정을 이용하여 필요한 부분만을 고농도로 주입할 수도 있다.On the other hand, when the impurity is implanted into the polycrystalline silicon in the process of FIG. 3, the impurity can be implanted as a photographic process using an image reversal method. It is also possible to inject high concentrations of the necessary parts using a photolithography process.

상기한 바와 같은 본 발명에 의하면 N+불순물 주입영역(3)과 P+불순물 주입영역(4)을 금속배선막을 이용하여 동시에 연결시킬 때, 어느 한 쪽의 접촉부위에서 서로 다른 불순물에 의해 형성되는 다이오드를 형성시키지 않고, 또한 각각의 접촉부위에서 안정된 저항성 접촉을 형성시킴으로서 낮은 접촉저항을 갖는 금속배선막을 형성시킬 수 있다. 이와 같은 본 발명 금속배선막 제조방법에 따르면 N+불순물 주입영역과 P+불순물 주입영역을 금속배선막으로 연결할 때 N+접촉부위 또는 P+접촉부위에서 저항의 증가를 방지하기 위해 별도의 배선막을 간접적으로 연결시키는 복잡한 제조공정이 생략될 수 있음과 더불어 N+불순물 주입영역과 P+불순물 주입영역을 낮은 접촉저항을 유지하면서 직접 연결을 가능하게 함으로써 반도체 설계 및 제조공정을 크게 간략화할 수 있는 이점이 있다.According to the present invention as described above, when the N + impurity implantation region 3 and the P + impurity implantation region 4 are simultaneously connected using a metal wiring film, a diode formed by different impurities at either contact portion It is possible to form a metal interconnection film having a low contact resistance by forming a stable ohmic contact at each contact portion without forming a. According to the method of manufacturing the metal interconnection film of the present invention, when the N + impurity implantation region and the P + impurity implantation region are connected to the metal interconnection layer, a separate wiring layer is indirectly used to prevent an increase in resistance at the N + contact region or the P + contact region. In addition, the complicated manufacturing process of connecting the N + impurity implantation region and the P + impurity implantation region can be directly connected while maintaining low contact resistance, thereby greatly simplifying the semiconductor design and manufacturing process. have.

Claims (4)

n형 웰이 형성되어 있는 p형 실리콘 기판상에 n+형 불순물 영역을 p형 실리콘 기판에, 그리고 p+형 불순물 영역이 n형 웰 내에 형성되어 있는 웨이퍼를 준비하는 단계; 상기 각 고농도 불순물 영역과 접촉하기 위한 접촉홀을 통하여 상기 두 고농도 불순물 영역을 상호 연결시키기 위한 실리콘을 도포하는 단계; 상기 다결정 실리콘층 위에 고융점 금속막을 도포하는 단계; 및 고온 열처리에 의해 고융점 금속막을 실리사이드막으로 형성함과 동시에 상기 각 고농도 불순물 영역과 인접한 부분의 다결정 실리콘으로 각각의 불순물을 확산시키는 단계로 구성되는 것을 특징으로 하는 반도체 장치의 금속배선막 제조방법.preparing a wafer in which an n + -type impurity region is formed in a p-type silicon substrate and a p + -type impurity region is formed in an n-type well on a p-type silicon substrate on which an n-type well is formed; Applying silicon for interconnecting the two high concentration impurity regions through contact holes for contacting the high concentration impurity regions; Coating a high melting point metal film on the polycrystalline silicon layer; And forming a high melting point metal film into a silicide film by high temperature heat treatment and simultaneously diffusing each impurity into polycrystalline silicon in a portion adjacent to each of the high concentration impurity regions. . 제1항에 있어서, 상기 고융점 금속막을 도포하는 단계전에, 상기 고농도 불순물 영역과 다결정 실리콘간의 접촉저항을 줄이도록 각각의 불순물과 동일한 도전형의 불순물을 추가로 주입하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 금속배선막 제조방법.The method of claim 1, further comprising, before the coating of the high melting point metal film, further implanting impurities of the same conductivity type as each impurity so as to reduce contact resistance between the high concentration impurity region and polycrystalline silicon. A metal wiring film manufacturing method of a semiconductor device. 제2항에 있어서, 추가의 불순물 주입은 역상(image reversal)법을 이용한 사진공정에 의해 이루어지는 것을 특징으로 하는 반도체 장치의 금속배선막 제조방법.The method of manufacturing a metal wiring film of a semiconductor device according to claim 2, wherein the additional impurity implantation is performed by a photographic process using an image reversal method. 제2항에 있어서, 추가의 불순물 주입은 전면 불순물 주입공정과 사진공정을 이용한 부분적 고농도 불순물 주입공정에 의해 이루어지는 것을 특징으로 하는 반도체 장치의 금속배선막 제조방법.The method of manufacturing a metal wiring film of a semiconductor device according to claim 2, wherein the additional impurity implantation is performed by a partial high concentration impurity implantation process using a front impurity implantation process and a photographic process.
KR1019880009642A 1988-07-29 1988-07-29 Metallic wire film manufacturing method of semiconductor device KR920000704B1 (en)

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KR1019880009642A KR920000704B1 (en) 1988-07-29 1988-07-29 Metallic wire film manufacturing method of semiconductor device
JP1197904A JPH02197120A (en) 1988-07-29 1989-07-29 Metal wiring method for semiconductor element

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KR1019880009642A KR920000704B1 (en) 1988-07-29 1988-07-29 Metallic wire film manufacturing method of semiconductor device

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