KR100219075B1 - Bipolar junction transistor and method of manufacturing the same - Google Patents
Bipolar junction transistor and method of manufacturing the same Download PDFInfo
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- KR100219075B1 KR100219075B1 KR1019960076263A KR19960076263A KR100219075B1 KR 100219075 B1 KR100219075 B1 KR 100219075B1 KR 1019960076263 A KR1019960076263 A KR 1019960076263A KR 19960076263 A KR19960076263 A KR 19960076263A KR 100219075 B1 KR100219075 B1 KR 100219075B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 14
- 125000006850 spacer group Chemical class 0.000 claims description 14
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조방법.Semiconductor device manufacturing method.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
얕고 좁은 접합 깊이를 갖는 에미터를 형성할 수 있는 바이폴라 접합 트랜지스터 및 그 제조방법을 제공하고자 함.An object of the present invention is to provide a bipolar junction transistor capable of forming an emitter having a shallow and narrow junction depth and a method of manufacturing the same.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
반도체 기판에 제1 도전형의 콜렉터를 형성하고, 콜렉터상부에 제2 도전형의 저농도 불순물이 도핑된 에피택셜층을 선택적으로 증착하여 베이스를 형성한 후, 소정부위의 베이스 상부에 제1 도전형의 고농도 불순물이 도핑된 에미터 커낵션을 형성한 다음, 상기 에미터 커낵션 측벽에 스페이서 형태의 제1 도전형의 에미터를 헝성하는 것을 특징으로 하는 바이폴라 접합 트랜지스터 및 그 제조방법을 제공하고자 함.A collector of the first conductivity type is formed on the semiconductor substrate, and a base is formed by selectively depositing an epitaxial layer doped with a low concentration impurity of the second conductivity type on the collector, and then the first conductivity type is formed on the base of the predetermined portion. To form an emitter connection doped with a high concentration of impurities, and then to form a spacer-type first conductivity type emitter on the sidewall of the emitter connection, and a method of manufacturing the bipolar junction transistor. .
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자 제조 공정중 바이폴라 접합 트랜지스터 및 그 제조방법에 이용됨.Used in bipolar junction transistor and manufacturing method in semiconductor device manufacturing process.
Description
본 발명은 바이폴라 접합 트랜지스터(Bipolar Junction Transistor) 및 그 제조방법에 관한 것이다.The present invention relates to a bipolar junction transistor and a method of manufacturing the same.
일반적으로, 바이폴라 트랜지스터는 트랜지스터 동작에 전자와 정공을 동시에 이용하는 트랜지스터를 말하며, 이와 상응하는 유니폴라(unipolar) 소자인 전계효과트랜지스터에 비하여 지연 시간이 짧기 때문에 빠른 동작 속도를 가지며 전력소비량도 전계효과트랜지스터에 비하여 작다.In general, a bipolar transistor refers to a transistor that simultaneously uses electrons and holes for transistor operation, and has a shorter delay time than a field effect transistor, a corresponding unipolar device, and thus has a high operating speed and a power consumption field effect transistor. Small compared to
이러한 바이폴라 접합 트랜지스터의 우수한 특성 때문에 캐쉬 메모리 등에 사용되는 바이-씨모스(BI-CMOS)에 많이 사용되고 있으며, 바이폴라 트랜지스터 시장의 급변화에 따라 고집적, 저전력 소비, 고주파를 가진 바이폴라 접합 트랜지스터가 요구되고 있다.Due to the excellent characteristics of such bipolar junction transistors, they are widely used in bi-CMOS (CMOS), which are used in cache memories. .
도1a 내지 도1d는 종래기술에 따른 바이폴라 접합 트랜지스터 제조 공정 단면도이다.1A to 1D are cross-sectional views of a bipolar junction transistor manufacturing process according to the prior art.
먼저, 도1a는 실리콘 기판(1)의 소정부위에 LOCOS(LOCal Oxidation of Silicon) 공정에 의해 소자 분리막(2)을 형성하고, 상기 실리콘 기판(1)에 대해 콜렉터 형성을 위한 N형 콜렉터 이온주입하여 콜렉터(3)를 형성한후, 전체구조 상부에 제1 폴리실리콘막(4)을 증착한 다음, 상기 제1 폴리실리콘막(4)에 대해 P형 불순물 도핑 공정을 실시하고, 전체구조 상부에 산화막(5)을 증착한 것을 도시한 것이다.First, FIG. 1A illustrates forming an isolation layer 2 on a predetermined portion of a silicon substrate 1 by a LOCOS (LOCal Oxidation of Silicon) process, and implanting an N-type collector ion into the silicon substrate 1 to form a collector. After forming the collector 3, the first polysilicon film 4 is deposited on the entire structure, and then the P-type impurity doping process is performed on the first polysilicon film 4, The deposition of the oxide film 5 is shown.
이어서, 도1b는 에미터 형성을 위한 마스크를 사용하여 상기 산화막(5) 및 제1 폴리실리콘막(4)을 식각하여 패터닝한 다음, 열공정을 진행하여 상기 제1 폴리실리콘막(4)내의 P형 불순물이 실리콘 기판(1)상의 콜렉터(3)내로 확산시켜 P+영역(6)을 형성하고, 전체구조 상부에 화학기상증착(Chemical Vapor Deposition; 이하 CVD라 칭함) 방식에 의한 CVD 산화막(7)을 형성한 것을 도시한 것이다.Subsequently, in FIG. 1B, the oxide film 5 and the first polysilicon film 4 are etched and patterned using a mask for forming an emitter, and then a thermal process is performed to form the first polysilicon film 4 in the first polysilicon film 4. P-type impurities are diffused into the collector 3 on the silicon substrate 1 to form the P + region 6, and the CVD oxide film is formed by chemical vapor deposition (hereinafter referred to as CVD) on the entire structure. 7) is shown.
이때, 상기 P+영역(6) 형성을 위한 열공정시 전체구조 상부에 열산화막(도시하지 않음)이 형성된다.At this time, a thermal oxide film (not shown) is formed on the entire structure during the thermal process for forming the P + region 6.
계속하여, 도1c는 반응성 이온 식각 공정에 의해 상기 콜렉터(3)상의 CVD 산화막(7)을 제거하여 측벽 산화막(7a)을 형성한 다음, 상기 콜렉터(3)상에 P형 불순물인 붕소(Boron)를 이온주입하여 P+영역(6)을 잇는 베이스(8)를 형성한 것을 도시한 것이다.Subsequently, FIG. 1C shows a sidewall oxide film 7a formed by removing the CVD oxide film 7 on the collector 3 by a reactive ion etching process, and then forming boron (P-type impurity) on the collector 3. ) Is implanted to form a base 8 connecting the P + regions 6.
마지막으로, 도1d는 상기 베이스(8)상에 고농도의 N형 불순물을 이온주입하여 N+영역을 형성하여 에미터-베이스 접합(9)을 이루고, 전체구조 상부에 고농도의 N헝 불순물이 도핑된 제2 폴리실리콘막을 증착한 다음, 이를 패터닝하여 에미터(10)를 형성한 것을 도시한 것이다.Finally, FIG. 1D shows an emitter-base junction 9 by ion implanting a high concentration of N-type impurities onto the base 8 to form an N + region, and doping of a high concentration of N Hung impurities over the entire structure. The second polysilicon film is deposited and then patterned to form the emitter 10.
이후, 콜렉터 및 베이스 콘택을 형성함으로써 NPN 바이폴라 접합 트랜지스터형성을 완료한다.Thereafter, NPN bipolar junction transistor formation is completed by forming collector and base contacts.
상기와 같이 진행되는 종래의 바이폴라 접합 트랜지스터 제조 공정은 에미터베이스 주사(Injection)와 에미터 전하저장(Charge Storage) 현상을 줄이기 위해서 얇은 베이스 폭(Thin Base Width)을 형성해야 하지만, 에미터내의 불순물의 확산 깊이가 크기 때문에 얇은 베이스위에 얕고 좁은 접합 깊이를 갖는 에미터의 형성은 불가능하다는 문제점이 있었다.In the conventional bipolar junction transistor manufacturing process as described above, a thin base width must be formed to reduce emitter base injection and emitter charge storage, but impurities in the emitter Due to the large diffusion depth of, there was a problem in that it was impossible to form an emitter having a shallow and narrow junction depth on a thin base.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 에미터-베이스 주사(Injection)와 에미터 전하저장(Charge Storage) 현상을 효과적으로 줄이면서 얕고 좁은 접합 깊이를 갖는 에미터를 형성할 수 있는 바이폴라 접합 트랜지스터 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is a bipolar junction that can form an emitter having a shallow and narrow junction depth while effectively reducing the emitter-base injection and emitter charge storage phenomenon It is an object of the present invention to provide a transistor and a method of manufacturing the same.
제1a도 내지 제1d도는 종래기술에 따른 바이폴라 접합 트랜지스터 제조 공정 단면도.1A to 1D are cross-sectional views of a bipolar junction transistor manufacturing process according to the prior art.
제2a도 내지 제2d도는 본 발명의 일실시예에 따른 바이폴라 접합 트랜지스터 제조 공정 단면도.2A to 2D are cross-sectional views of a bipolar junction transistor fabrication process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘 기판 20 : 소자 분리막10 silicon substrate 20 device isolation film
30 : N-콜렉터 40 : N+콜렉터30: N - collector 40: N + collector
50 : 에피택셜층 50a : P-베이스50: epitaxial layer 50a: P - base
60 : LPCVD 산화막 70 : 제1 폴리실리콘막60: LPCVD oxide film 70: first polysilicon film
70a : 에미터 커낵션 80 : 제2 폴리실리콘막 스페이서70a: emitter connection 80: second polysilicon film spacer
80a : 에미터 90 : 산화막 스페이서80a: emitter 90: oxide spacer
100 : 실리사이드막 110 : 에미터-베이스 접합100: silicide film 110: emitter-base junction
120 : 포토레지스트 페턴120: photoresist pattern
상기 목적을 달성하기 위하여 본 발명은 반도체 기판상에 형성된 제1 도전형의 콜렉터;상기 제1 도전형의 콜렉터상에 형성된 제2 도전형의 베이스;소정부위의 상기 제2 도전형의 베이스 상부에 형성된 제1 도전형의 에미터 커낵션;상기 에미터 커낵션 측벽에 스페이서 형태로 형성된 제1 도전형의 에미터를 구비해서 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a collector of a first conductivity type formed on a semiconductor substrate; a base of a second conductivity type formed on a collector of the first conductivity type; An emitter connection of the first conductivity type formed; and the emitter of the first conductivity type formed in the form of a spacer on the sidewall of the emitter connection.
또한, 본 발명은 반도체 기판상에 제1 도전형의 콜렉터를 형성하는 단계;전체구조 상부에 선택적 에피택셜층을 형성하고, 상기 선택적 에피택셜층에 대해 저농도의 제2 도전형의 불순물을 이온주입하여 베이스를 형성하는 단계;전체구조 상부에 제1 절연막 및 에미터 커낵션 형성용 전도막을 형성하고, 상기 에미터 커낵션 형성용 전도막에 대해 고농도의 제1 도전형의 불순물을 이온주입하는 단계;에미터 커낵션 형성용 마스크를 사용하여 상기 에미터 커낵션 형성용 전도막을 식각하여 에미터 커낵션을 형성하는 단계;전체구조 상부에 에미터 형성용 전도막을 형성하고, 마스크없이 전면식각하여 상기 에미터 커낵션 측벽에 스페이서 형태로 잔류시키는 단계; 전체구조 상부에 제2 절연막을 형성하고, 마스크없이 전면식각하여 상기 에미터 형성용 전도막 측벽에 제2 절연막 스페이서를 형성하는 단계; 전체구조 상부에 금속막을 형성하는 단계;및 상기 베이스 및 에미터 커낵션에 자기 정렬 실리사이드막을 형성함과 동시에 상기 에미터 커낵션내의 제1 도전형의 불순물을 상기 에미터 Å 전도막내로 확산시켜 에미터를 형성하고, 상기 에미터로 확산된 불순물이 하부의 베이스로 확산되어 에미터-베이스 접합을 형성하는 단계를 포함하는 것을 특징으로 한다.In addition, the present invention comprises the steps of forming a collector of the first conductivity type on the semiconductor substrate; forming an optional epitaxial layer on the entire structure, the ion implantation of a low concentration of the second conductivity type impurities to the selective epitaxial layer Forming a base by forming a first insulating film and a conductive film for forming an emitter connection on the entire structure, and ion implanting impurities of a first conductivity type in a high concentration with respect to the conductive film for forming an emitter connection Etching the conductive layer for forming the emitter connection using an emitter connection forming mask to form an emitter connection; forming an emitter forming conductive layer on the entire structure, and etching the entire surface without a mask Remaining in the form of a spacer on the emitter connection sidewalls; Forming a second insulating film spacer on the entire structure, and etching the entire surface without a mask to form a second insulating film spacer on the sidewalls of the emitter forming conductive film; Forming a metal film on the entire structure; and forming a self-aligned silicide film on the base and emitter connections and simultaneously diffusing impurities of the first conductivity type in the emitter connections into the emitter Å conductive film. And forming an emitter and the impurities diffused into the emitter to form an emitter-base junction.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도2a 내지 도2d는 본 발명의 일실시예에 따른 바이폴라 접합 트랜지스터 제조 공정 단면도이다.2A through 2D are cross-sectional views illustrating a bipolar junction transistor manufacturing process according to an exemplary embodiment of the present invention.
먼저, 도2a는 실리콘 기판(10)의 소정부위에 LOCOS(LOCal Oxidation of Silicon) 공정에 의해 소자 분리막(20)을 형성하고, 콜렉터 형성을 위해 N형 불순물을 저농도 콜렉터 이온주입하여 저농도 콜렉터 이온주입 영역(30)을 형성한 후, 이어 콜렉터 형성을 위한 고농도 콜텍터 이온주입 공정을 실시하여 고농도 콜렉터 이온주입 영역(40)을 형성한 다음, 열처리하고, 상기 실리콘 기판(10) 표면에 300Å 내지 700Å 정도 두께의 에피택셜충(50) 선택적으로 성장시킨 것을 도시한 것이다.First, FIG. 2A illustrates a device isolation film 20 formed on a predetermined portion of a silicon substrate 10 by a LOCOS (LOCal Oxidation of Silicon) process. After forming the region 30, a high concentration collector ion implantation process for forming a collector is then performed to form a high concentration collector ion implantation region 40, and then subjected to heat treatment. It shows that the epitaxial worms (50) selectively grown to a certain thickness.
이어서, 도2b는 상기 에피택셜충에 대해 P-불순물을 이온주입하여 P-베이스(Base)(50a)를 형성하고, 전체구조 상부에 LPCVD(Low Pressure Chemical Vapor Deposition; 이하 LPCVD라 칭함) 방식에 의해 200Å 내지 500Å 정도 두께의 LPCVD 산화막(60)을 형성하고, 상기 LPCㄲ) 산화막(60) 상부에 제1 폴리실리콘막(70)을 증착한 후, 고농도 N형 불순물(N+)올 도핑한 다음, 전체구조 상부에 포토레지스트를 도포하고, 소정의 마스크를 사용한 포토리쏘그라피 공정에 의해 포토레지스트 패턴(120)을 형성한 것을 도시한 것이다.Subsequently, FIG. 2B is a P - base 50a formed by ion implantation of P − impurities into the epitaxial worm, and then referred to as a low pressure chemical vapor deposition (LPCVD) method on the entire structure. LPCVD oxide film 60 having a thickness of about 200 kV to about 500 kW was formed, the first polysilicon film 70 was deposited on the LPC ㄲ) oxide film 60, and then doped with a high concentration N-type impurity (N + ). Next, a photoresist is coated on the entire structure and a photoresist pattern 120 is formed by a photolithography process using a predetermined mask.
계속해서, 도2c는 상기 포토레지스트 패턴(120)을 식각마스크로 상기 제1 폴리실리콘막(70) 및 LPCVD 산화막(60)을 차례로 식각하여 N+에미터 커낵션(70Å)을 형성하고, 상기 포토레지스트 패턴(120)을 제거한 후, 전체구조 상부에 불순물이 도핑되지 않은 제2 폴리실리콘막을 LPCVD 방식에 의해 100Å 내지 500Å 정도의 두께로 증착한 다음, 상기 제2 폴리실리콘막을 마스크없이 전면식각하여 상기 LPCVD 산화막(60) 및 제1 폴리실리콘막(70) 측벽에 제2 폴리실리콘막 스폐이서(80)를 형성한 것을 도시한 것이다.Subsequently, in FIG. 2C, the first polysilicon layer 70 and the LPCVD oxide layer 60 are sequentially etched using the photoresist pattern 120 as an etch mask to form an N + emitter connection 70 ′. After the photoresist pattern 120 is removed, a second polysilicon film not doped with impurities is deposited on the entire structure to a thickness of about 100 kPa to about 500 kPa by LPCVD, and then the entire surface of the second polysilicon film is etched without a mask. The second polysilicon layer spacer 80 is formed on the sidewalls of the LPCVD oxide layer 60 and the first polysilicon layer 70.
마지막으로, 도2d는 전체구조 상부에 1000Å 내지 3000Å 정도 두께의 산학막을 형성하고, 마스크없이 전면 식각하여 상기 제2 폴리실리콘막 스페이서(80) 측벽에 산화막 스페이서(90)를 형성한 후, 전체구조 상부에 금속막을 증착하고, 상기 금속막 형성 공정까지 완료된 웨이퍼에 대해 급속 열처리(Rapid Thermal Anneal)공정을 실시하여 상기 P-베이스(50a) 및 N+콜렉터 커낵션(70a)상의 상기 금속막을 상 변환시켜 실리사이드막(100)을 형성한 다음, 상변환되지 않은 금속막을 제거한 것을 도시한 도시한 것이다.Finally, Figure 2d is formed on the top of the overall structure of the film thickness of 1000 ~ 3000 산, the entire surface is etched without a mask to form the oxide film spacer 90 on the sidewall of the second polysilicon film spacer 80, the overall structure A metal film is deposited on the upper surface, and a rapid thermal annealing process is performed on the wafer completed up to the metal film forming process to phase-convert the metal film on the P - base 50a and the N + collector connection 70a. To form the silicide film 100, and then remove the phase-converted metal film.
이때, 상기 금속막의 상변환 위한 급속 열처리 공정시 N+콜렉터 커낵션(70a)의 N형 불순물이 상기 제2 폴리실리콘막 스페이서(80)에 확산되어 N-에미터(80a)를 형성함과 동시에 상기 N-에미터(80a)의 불순물이 하부의 P-베이스(50a)로 확산되어 1000Å 이하의 N-에미터-베이스 접합(110)을 형성한다.At this time, the N-type impurity of the N + collector connection 70a is diffused into the second polysilicon film spacer 80 during the rapid heat treatment process for phase conversion of the metal film to form the N − emitter 80a. Impurities in the N - emitter 80a diffuse into the lower P - base 50a to form an N - emitter-base junction 110 of 1000 mW or less.
이상에서 설명한 본 발명은 전술한 실시예 및 침부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 번형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, changes, and modifications can be made within the scope without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 본 발명은 매우 좁은 폭의 에미터 영역 및 얕은 에미터-베이스 접합을 형성함으로써 매우 얇은 베이스를 가진 바이폴라 접합 트랜지스터를 형성할 수 있으며, 이에 따라 낮은 전력 소비 및 높은 주파수 대역을 가지는 바이폴라 접합 트랜지스터 제조를 가능하게 하는 효과가 있다.As described above, the present invention can form a bipolar junction transistor having a very thin base by forming an emitter region and a shallow emitter-base junction of a very narrow width, and thus a bipolar junction having a low power consumption and a high frequency band. There is an effect of enabling transistor manufacturing.
Claims (7)
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