JP2002184783A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a bipolar transistor wherein a lead base electrode can be connected to an epitaxial silicon layer in a low damage process in a simple and convenient manner. SOLUTION: In forming a base/emitter, damage of a surface of the epitaxial silicon layer 3 by etching can be eliminated by stopping dry etching of a silicon oxide film 11 and thereafter wet etching the film. Further, deformation of a polysilicon film 12 as a lead base electrode can be enhanced by heating the film at an ultra-high vacuum level (of 1×10-4 to 1×10-5 Pa). As a result, self alignment enables the base electrode to be connected to the silicon layer 3. A part 18 contacted with the silicon layer 3 is formed to have an eaves structure due to the above wet etching, so that the contact area of the part 18 with the base electrode can be made large and thus a base resistance can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bipolar transistor requiring high-frequency operation.

[0002]

2. Description of the Related Art In recent years, bipolar transistors mounted on a silicon semiconductor substrate have recently been developed using HBT (Hetero B).
Ipolar Transistors) have been put to practical use, and high-speed operation at an operating frequency of 50 GHz or more has become possible. Under such circumstances, simplification of the manufacturing method of the bipolar transistor is urgently required.

[0003] The present invention relates to a method for easily connecting a lead base electrode and a base region in a bipolar transistor. As a conventional technique very similar to the present invention, a technique described in Japanese Patent Application Laid-Open No. 6-104271 will be described with reference to FIGS.

As shown in FIG. 7, an N ⁺ buried region 102 is formed in a P-type silicon substrate 101 and an N-type epitaxial epitaxial silicon layer 1 is formed on the entire surface of the substrate.
Grow 03. This epitaxial silicon layer 10
3 is also a collector region. The above-mentioned epitaxial silicon layer 103 is selectively oxidized to form a field oxide layer 104.
To form Then, after forming a resist pattern, an N ⁺ -type impurity is ion-implanted to form an N ⁺ -type collector contact region 105 so as to reach the N ⁺ buried region 102.

Next, a U-groove element isolation region 107 is formed, and a side surface of the U-groove is thermally oxidized to form an insulating film 108.
The trench is filled with a polysilicon layer 109. Then, the upper portion of the polysilicon layer 109 is thermally oxidized to form an oxide layer integrated with the field oxide layer.

Next, as shown in FIGS. 7 and 8 (a),
The N-type epitaxial silicon layer 103 where there is no field insulating layer 104 is thermally oxidized to form a silicon oxide film 1.
11 is formed. A polysilicon film 112 is grown on the entire surface by a chemical vapor deposition (CVD) method, and impurities (for example, B) are ion-implanted therein. Next, an insulating film 113 is formed on the entire surface by a CVD method. A resist layer 114 is applied on the insulating film 113, and an emitter contact opening 115 is formed by exposure and development.
To form The insulating layer 113 that is not covered with the resist mask 114 is removed by etching by reactive ion etching (RIE), and the polysilicon base electrode 112 is removed by etching by RIE using an etching gas for etching polysilicon. The emitter contact 116 is opened. At this stage, the silicon oxide film 1
11 remains.

Further, the silicon oxide film 111 is etched and removed by RIE using an etching gas for an oxide film to complete a base contact 117 for forming an intrinsic base region, as shown in FIG. 8B.

Next, in an H ₂ atmosphere at normal pressure,
After heating (annealing) at 900 ° C. for 5 to 20 minutes, FIG.
As shown in (c), the end of the impurity-doped polysilicon film 112 serving as the extraction base electrode is reflowed,
Contact part 1 that contacts epitaxial silicon layer 103
18 are formed.

Next, a P-type impurity 119 (for example, B) is
Ion implantation into the epitaxial silicon layer 103 through the base contact 117 forms the intrinsic base region 121. An annealing process is performed after the ion implantation, so that the base region 121 expands in the lateral direction and extends below the insulating layer 111. At this time, the P-type impurity is transferred from the polysilicon contact portion 118 to the epitaxial silicon layer 103 in a solid phase. Spread.

Then, as shown in FIG. 8D, the side wall insulating film 122 of the base contact 117 is connected to the contact portion 118.
Is formed so as to cover. After that, a polysilicon layer is grown, and an N-type impurity is solid-phase diffused into the base region 121 from the emitter polysilicon layer 123 having a predetermined pattern by a normal photolithography method.
24 are formed.

[0011] Then, as shown in FIG.
3 is selectively etched by RIE, a collector contact hole and a base contact hole are opened, and a metal layer is sputtered on the entire surface. The metal layer is formed by photolithography and RIE. The base electrode 127 and the emitter electrode 128 are formed to form a bipolar transistor.

[0012]

However, in the above-described conventional method, when the emitter region and the base region are formed, and when the silicon oxide film 111 is removed by etching after the opening of the emitter contact 116, the epitaxial method is performed by dry etching. Etching damage occurs in the silicon layer 103, and after the transistor is formed, a leak occurs on the low current side, which causes a problem that the yield of the transistor is reduced.

Further, in the above-mentioned conventional technique, since the etching is performed in an H ₂ atmosphere, the dopant is removed from the base polysilicon or an insulating film such as an oxide film is reduced and the film quality is deteriorated.

A main object of the present invention is to prevent the epitaxial silicon layer 103 from being damaged during the formation of the emitter section and the base section, and to reduce the base resistance by increasing the contact area with the extraction base electrode. By forming the emitter portion and the base portion without causing the dopant to escape from the polysilicon film 12 serving as the extraction base electrode, there is no low current leakage even after the transistor is formed.
Another object of the present invention is to provide a transistor which is a simple manufacturing process, has a high yield, and has excellent high-frequency characteristics.

[0015]

According to a method of manufacturing a semiconductor device of the present invention, a first conductive type semiconductor layer serving as a collector region is formed on a semiconductor substrate, and a first insulating layer and a second insulating layer are formed on the semiconductor layer. Forming a two-conductivity-type extraction base electrode and a second insulating layer in this order; selectively dry-etching the second insulation layer and the extraction base electrode to form a through-hole; A step of dry-etching the first insulating layer halfway through the film thickness, and performing a wet etching after the dry etching to remove the first insulating layer remaining in the through-hole portion and to form a first insulating layer under the lead base electrode. A step of side-etching a layer; a step of deforming the extraction base electrode by heating to connect to the semiconductor layer in a region of the side-etch; Doping a second conductivity type impurity through a hole to form a base region on the surface of the semiconductor layer; forming a side wall insulating layer on a side surface of the extraction base electrode; and passing through a through hole inside the side wall insulating layer. Forming an emitter region by doping first conductivity type impurities; and forming an emitter electrode in the through hole.

According to the present invention, the manufacturing steps of the bipolar transistor are simplified and the number of steps is reduced.

Here, the first insulating layer has a thickness of 10 nm.
It is a silicon oxide film in a range of ４０40 nm. The amount of the side etch is set to be 200 nm or more. Further, the extraction base electrode is a polycrystalline silicon layer containing impurities.

The heating is performed at 10 ^-4 Pa to 10 ^-5 P
a, the temperature of the heating is from 750 ° C.
Set to be in the range of 900 ° C.

Under the above numerical limitation, the extraction base electrode can be very easily deformed and easily connected to the semiconductor layer.

By forming the emitter portion and the base portion by the above-described method, it becomes possible to manufacture a transistor having no low current leakage even after forming the transistor, having a high yield, and having excellent high-frequency characteristics.

[0021]

FIG. 1 shows an embodiment of the present invention.
This will be described in detail with reference to FIGS. FIG. 1 shows a cross-sectional structure of a bipolar transistor. 2 to 6
FIG. 4 is a cross-sectional view of each step for explaining the manufacturing process.

As in the case of the conventional technique described with reference to FIG. 1, an N ⁺ buried region 2 is formed in a P-type silicon substrate 1, and an N-type epitaxial silicon layer 3 as a semiconductor layer is grown on the entire surface of the substrate. . This epitaxial silicon layer 3 is a collector region. This epitaxial silicon layer 3 is selectively oxidized to form a field oxide layer 4. After a resist pattern is formed, N-type impurities are ion-implanted and pressed to form an N ⁺ -type collector contact region 5.

Next, as shown in FIGS. 1 and 2, the N-type epitaxial silicon layer 3 as a semiconductor layer is thermally oxidized to form a silicon oxide film 11 as a first insulating layer to a thickness of 10 nm.
It is formed with a thickness of 40 nm. Then, a polysilicon film 12 is formed to a thickness of 100 nm to 300 nm on the entire surface by the CVD method, and impurities (for example, B) are added thereto with an acceleration energy of 5 to 5 nm.
50 KeV, dose amount 1 × 10 ¹⁴ -1 × 10 ¹⁶ / cm ²
The ion implantation is performed under the following conditions. This polysilicon film 12 becomes a lead base electrode. Here, the silicon oxide film 1
The reason why 1 is set to 10 nm or more is to ensure insulation between the epitaxial silicon layer 3 serving as the collector region and the polysilicon film 12 serving as the extraction base electrode. The reason why the thickness of the silicon oxide film 11 is set to 40 nm or less is to facilitate connection between the polysilicon film 12 described later and the epitaxial silicon layer 3.

Next, an insulating film 13 (for example, a nitride film) serving as a second insulating layer is formed on the entire surface by CVD to a thickness of 100 nm to 50 nm.
0 nm is formed. A resist layer 14 is formed on the insulating film 13.
Is applied, and an emitter opening 15 corresponding to the emitter portion and the base portion is formed by exposure and development. This resist mask 1
Then, the insulating layer 13 not covered with the insulating film 13 is removed by etching by the RIE method.
Is removed by etching to open an emitter contact 16 to be a through hole. At this stage, the silicon oxide film 1
1 remains. At this time, the etching conditions for the polysilicon are determined so that the remaining oxide film is about 5 nm to 10 nm.

Thereafter, the remaining film of the silicon oxide film 11 is etched by wet etching to complete a base contact 17 for forming an intrinsic base region as shown in FIG. At this time, the etching time is controlled so that the silicon oxide film 11 is side-etched in the lateral direction over an amount of 200 nm or more. Thus, an eave is formed below the polysilicon film 12.

Next, when heated at 750 ° C. to 900 ° C. for 5 to 30 minutes under ultra-high vacuum (in the range of 10 ^-4 to 10 ^-5 Pa), as shown in FIG. The end of the impurity-doped polysilicon film 12 is deformed to form a contact portion 18 connected to the epitaxial silicon layer 3 at the above-mentioned side-etch region, that is, at the eaves. Then, the temperature is raised to 800 ° C. to 1000 ° C.,
When heating is performed for 2 minutes, impurities diffuse in the solid phase into the epitaxial silicon layer 3 and low-resistance contact becomes possible.

The end of the impurity-doped polysilicon film 12 serving as the extraction base electrode is subjected to the above-described heat treatment.
When connecting to the epitaxial silicon layer 3, the thickness of the silicon oxide film 11 is very important. When the film thickness is increased, the above connection does not occur. In the trial experiment of the inventor, the upper limit of the film thickness is 40 nm. Also, the shape of the eaves is important. If the amount of the side etch is small, the connection does not occur. The amount of side etch is 2
00 nm or more is essential.

Although the mechanism of the deformation of the end portion of the polysilicon film 12 due to the heating according to the present invention is not clear at present, it is considered that it depends on the change of the crystal grain boundary of the polysilicon film. Then, when heating in which a trace amount of oxygen or moisture is present, a slight oxide film is formed on the surface of the polysilicon film 12, and the above-mentioned deformation is eliminated. For this reason, heat treatment in a high vacuum becomes very effective. Here, the degree of vacuum is preferably in the range of 10 ^-4 to 10 ^-5 Pa.

Next, as shown in FIG.
(For example, B) is ion-implanted into the epitaxial silicon layer 3 through the emitter contact 16 to form the intrinsic base region 21. An annealing process is performed after the ion implantation, so that the base region 21 also diffuses in the lateral direction and extends below the insulating layer 11.
8 that the P-type impurity is
Solid phase diffusion. Thus, the polysilicon film 12 serving as the extraction base electrode and the base region 21 are completely connected.

Then, as shown in FIG. 6, a sidewall insulating film 22 is formed on the sidewall of the emitter contact 16 described above. Thereafter, a polysilicon layer is grown, and an N-type impurity (for example, As) is ion-implanted into the polysilicon layer under the conditions of an acceleration energy of 20 to 70 keV and a dose of 3 × 10 ¹⁶ / cm ² . Thereafter, an emitter polysilicon layer 23 having a predetermined pattern is formed by a normal photolithography method, and an N-type impurity is solid-phase diffused from the emitter polysilicon layer 23 into the base region 21 by heat treatment, thereby forming the emitter region 24. Form.

Then, as shown in FIG. 1, an insulating interlayer film 25 (for example, a BPSG film) is grown and selectively etched by RIE to form collector, base and emitter contact holes, and a collector having a predetermined wiring pattern is formed. The electrode 26, the base electrode 27, and the emitter electrode 28 are formed by a normal process.

In this manner, the base region and the emitter region are formed by a self-alignment method, and a bipolar transistor is manufactured.

In the formation of the extraction base electrode, an in-situ impurity-doped polysilicon film growth method may be used instead of the non-doped polysilicon film 12 growth and the impurity ion implantation. Similarly,
In the formation of the extraction emitter section, instead of growing the non-doped polysilicon film 23 and implanting the impurity ions, a method of growing the impurity-doped polysilicon film in-situ may be used.

In the above-described embodiment, the base region may be formed not in the silicon (Si) layer but in the Si-Ge layer. In this case, it is an HBT.

[0035]

As described above, according to the present invention, in the manufacture of a bipolar transistor, the extraction base electrode is deformed by heat treatment and connected to the semiconductor layer serving as the base region. Here, the thickness of the silicon oxide film interposed between the extraction base electrode and the semiconductor layer is set to 10
nm to 40 nm. Then, part of the silicon oxide film is etched by wet etching,
The side etch amount generated at that time is set to be 200 nm or more.

The heat treatment is performed at 10 ⁻⁴ Pa to 10 ⁻⁵ Pa.
It is performed within the range of the vacuum degree of Pa, and the temperature of the heat treatment is 750 ° C.
The temperature is set so as to be in a range of ９００900 ° C.

According to the present invention, the manufacturing steps of the bipolar transistor are simplified and the number of steps is reduced.

Further, by forming the base portion by the above-described method, it becomes possible to manufacture a transistor having no low current leakage even after forming the transistor, having a high yield, and having excellent high-frequency characteristics.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a bipolar transistor manufactured by a manufacturing method according to the present invention.

FIG. 2 is an enlarged cross-sectional view of a bipolar transistor when a polysilicon layer of an extraction base electrode is etched in a manufacturing process according to the present invention.

FIG. 3 is an enlarged sectional view of a bipolar transistor when a first insulating layer is etched to form a base contact in a manufacturing process according to the present invention.

FIG. 4 is an enlarged cross-sectional view of a bipolar transistor when a lead base electrode and an epitaxial silicon layer are connected in a manufacturing process according to the present invention.

FIG. 5 is an enlarged cross-sectional view of the bipolar transistor when a base region is formed in a manufacturing process according to the present invention.

FIG. 6 is an enlarged sectional view of the bipolar transistor when an emitter region is formed in a manufacturing process according to the present invention.

FIG. 7 is a schematic sectional view of a bipolar transistor manufactured by a conventional manufacturing method.

FIG. 8 is an enlarged cross-sectional view of a conventional bipolar transistor in a manufacturing process of the bipolar transistor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 P-type silicon substrate 2 N ⁺ buried region 3 epitaxial silicon layer 4 field oxide layer 5 collector contact region 11 silicon oxide film 12 polysilicon film 13 insulating film 14 resist layer (resist mask) 15 emitter opening 16 emitter contact 17 base contact DESCRIPTION OF SYMBOLS 18 Contact part 19 P-type impurity 21 Intrinsic base region 22 Side wall insulating film 23 Emitter polysilicon layer 24 Emitter region 25 Insulating interlayer film 26 Collector electrode 27 Base electrode 28 Emitter electrode

Claims (6)

[Claims] 2. A semiconductor device comprising: a first substrate on a semiconductor substrate;
Forming a conductive type semiconductor layer, forming a first insulating layer, a second conductive type lead base electrode and a second insulating layer on the semiconductor layer in this order; The base electrode is selectively dry-etched to form a through hole, and subsequently,
A step of dry-etching the first insulating layer halfway through the film thickness; a step of performing wet etching after the dry etching to remove the first insulating layer remaining in the through-hole portion; A step of side-etching the insulating layer of (a), a step of deforming the extraction base electrode by heating to connect to the semiconductor layer in a region of the side-etch, and doping a semiconductor of the second conductivity type through the through hole. Forming a base region on the surface of the layer, forming a side wall insulating layer on a side surface of the extraction base electrode,
Doping an impurity of a first conductivity type through a through hole inside the sidewall insulating layer to form an emitter region; and forming an emitter electrode in the through hole.
A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the first insulating layer has a thickness of 10 nm to 4 nm.
2. The method according to claim 1, wherein the silicon oxide film has a thickness of 0 nm. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the amount of the side etch is 200 nm or more. 4. The method for manufacturing a semiconductor device according to claim 1, wherein said extraction base electrode is a polycrystalline silicon layer containing impurities. 5. The manufacturing of a semiconductor device according to claim 1, wherein the heating is performed in a range of a vacuum degree of 10 ⁻⁴ Pa to 10 ⁻⁵ Pa. Method. 6. The method according to claim 5, wherein the heating temperature is set in a range of 750 ° C. to 900 ° C.