KR930010354B1 - Operating circuit of galois field - Google Patents

Abstract

An operational circuit on Galois field (2m) includes first and second input selection terminals, a comparator, first and second flip-flop, an operational portion having a multiplying unit and a dividing unit, a multiplication & division selecting portion, and an output selecting portion, thereby heightening packing density of a chip serving for correcting an error and reducing complexity of a hardware without using ROM or PLA.

Description

Computation Circuit on Galoache

1 is a block diagram of a multiplication circuit on a conventional galloche.

2 is a block diagram of a division circuit on a conventional gallo body.

3 is a block diagram of an arithmetic circuit on a galloche according to the present invention.

4 is an implementation circuit of part A of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to arithmetic circuits for multiplication and division on Galois field GF (2 ^m ), and more particularly to arithmetic circuits on galois for error correction in digital signal processing.

In the related art, a cross-interleaving technique has been used for dataword error correction of a digital signal to be recorded when an error occurs in a reproduction pulse code modulation (PCM) signal. In the error correction technique using this technique, the output of the determinant error correction coding apparatus of RS (Reed-Solomon) is represented by an element combination of gallo GF ( ^2m ).

Computation circuit on a galloche using ROM (Read Only Memory) or PLA (Programmable Logic Array) and an addition circuit to calculate a digital data word that can be regarded as an element of galloche is disclosed in Korean Patent Application Publication No. 90-5435. It is described in the issue. This is the element of Galoache GF (2 ^m ) ⁱ and an operation circuit for computing the digital data word constituting ^j is provided. ⁱ and ^j is supplied to the input of a conversion circuit such as ROM, and the conversion circuit is provided with each output index i and j Power of ⁱ and It provides the index i and j) of the ^j. These indices i and j are combined in the addition circuit of the addition combination circuit, and their sum i + j is added to the inverse conversion circuit. This circuit operates in a complementary manner to the conversion circuit and has two input elements. ⁱ and Multiplication output according to multiplication of ^j gives ^{(i + j)} .

If the addition combination circuit includes an inversion circuit and is connected between the conversion circuit and the addition circuit, an element ⁱ is another element calculated by ^{j (ij)} can be found. In this case ^Divide by (i.e., identify whether ^j is zero) ^j = 0). And, counting if ^j = 0 Change ^(ij) to 0.

Such conventional circuits are shown in FIGS. 1 and 2, respectively. Where (1A) is an element represents a conversion ROM which generates its index i when ⁱ is supplied (1B) ^The conversion ROM which generates the index j when ^j is supplied is shown. The exponents i and j are m-bit binary codes, respectively. (2) denotes an addition circuit of (mod, 2 ^m -1), (3) denotes an inverse conversion ROM that generates power output data having an exponent input thereto, and (4A) denotes a conversion ROM (1B). An inverting circuit for inverting the exponent j outputted from and supplying it to the addition circuit 2 is shown. You may use PLA instead of ROM (1A) (1B) (3). The conversion circuit 1A (1B) and the inverse conversion circuit 3 include any accessible storage device, which uses a ROM. In the conventional multiplication circuit shown in FIG. 1, the output i + j in which the exponents i and j generated in each of the conversion ROMs 1A and 1B are added by the addition circuit 2 is transferred to the inverse conversion ROM 3. Input, multiplied output (as output data) ^{i + j} = ⁱ ㆍ ^j ) The conventional division circuit shown in FIG. 2 inverts the index j output from the conversion ROM 1B by the inversion circuit 4A, supplies it to the addition circuit 2, and outputs the output ij of the inverse conversion ROM 3. ) And divide output as output data. ^ij = ⁱ / ^j ) The addition circuit 2 and the inversion circuit 4A constitute an addition combination circuit.

In the conventional technology, the digital signal processing processor uses the RS (Reed-Solomon) code for error correction in order to multiply and divide using the conversion / inverse conversion ROM or PLA, thereby increasing the area of the chip. It caused a loss.

Accordingly, it is an object of the present invention to provide an arithmetic circuit that can multiply and divide on a Galloiche in hardware without using ROM or PLA.

In the description of the present invention, the description of gallosome GF (p ^m ), which can be expressed in any of a vector or a circuit group, is described in the above-mentioned Korean Patent Publication No. 90-5435. If an error occurs, the correction circuit uses a syndrome to find two error positions and error values. In this case, if only two syndromes are obtained,

SO = ei + ej SI = ⁱ ei + ^j ej

If the exact position of the error is known in the above equation, the error values can be obtained as follows.

As can be seen from this calculation equation, an addition, multiplication, and control circuit on the galloise is required to obtain the error values. The addition circuit can be easily implemented by using an Exclusive-OR gate. Therefore, the present invention is applied to winning and dividing. In the error detection correcting code, if 1 word is 8 bits and 8 bits of GF (2 ⁸ ) is used, the contract polynomial is expressed as F (X) = X ⁸ + X ⁴ + X ³ + X ² +1, which is 255. It is a patrol army of.

Less than ⁱ , ^The present invention for performing multiplication and division using ^j is described below with reference to the accompanying drawings. In the arithmetic circuit on Galoache GF (2 ^m ), patterns in which the input patterns selected at the first and second input selection stages 10A and 10B for selecting an input and the second input selection stage 10B are memorized First and second flip-flops 11A and 11B controlled by the output signal of the comparison unit 14 and the NOOR gate NOR which inputs the output of the comparison unit 14 and the first input selection Computation unit 13 for multiplying and dividing the input of stage 10A, multiplication and division selecting unit 16 for selecting multiplier 13B and divider 13A among the calculation units 13, and comparison unit 14 And an output selector 15 for selectively outputting the arithmetic value selected by the multiplication and division selector 16 according to the output control signal of "

The first and second input selection stages 10A and 10B and the multiplication and division selection unit 16 are constituted by multiplexers, and the comparison unit 14 once receives the input selected by the second input selection stage 10B. It consists of an Exclusive-Orgate (EX-OR) having the other end of information stored in the memory. Here, input 1 is first selected by the first input selection stage 10A, and input 2 is first selected by the second input selection stage 10B.

The operation and the effect of the present invention will be described in detail. The division unit 13A is selected by the multiplication and division control signal C in the multiplication and division selection unit 16 of FIG. When the element α ⁱ is input to the first input selection terminal 10A and the first flip-flop 11A is enabled, the element a ¹ is multiplied by α (2 ^m -1) ^-n. The value is applied to the first flip flop 11A.

Here, in Galoache GF (2 ^m ), it is a traversal group of the rank 255 with m = 8. (2 ^m -1) ^{-n, which} means ⁱ ) ^The result of multiplying ^255-n returns the element ( ⁱ ) ^The result divided by ⁿ is shown. At this time, the comparison unit 14 selects the element selected in the second input selection terminal 10B ( ^j ) is compared with the pantones of the elements stored in the comparator 14. The memorized elements of the comparator 14 are elements a ⁰ to a ^n-1 , and these elements and the input element ( ^j ) Ex-OR the pattern. The pattern and element of the comparator 14 ^When comparing ^j ), if there is no matching pattern, the output value of the noah gate which inputs the output of the comparing unit 14 is ＂1＂, enabling the first and second flip-flops 11A and 11B. Let's do it. When the first and second flip-flops 11A and 11B are enabled, the element ( ⁱ , ^j ) The value multiplied by (2 ^m −1) ⁻ⁿ is fed back to the first and second input selection stages 10A and 10B.

However, when there is a matching pattern when the element selected in the second input terminal 10B is compared with the elements of the comparator 14 during the above process, the output value of the noah gate as the input of the comparator 14 is ＂ It becomes 0ms and disables the 1st, 2nd flip-flop. At this time, the first input selection stage 10A has an element that has been fed back before the flip-flop is disabled. In the division unit 13A, this element is (2 ^m -1) ^-0 to Calculate with (2 ^m -1)-(n-1) respectively.

The values calculated by the divider 13A are calculated by the output selector 15 according to the control signal of the comparator 14. ⁱ / ^j ) is printed.

When the multiplication section B is selected by the multiplication and division selection signal C from the microprocessor (not shown) in the configuration shown in Fig. 3, the first input selection stage 10A is selected. To the selected input value ⁰ to multiplying ⁿ (n = 1, 2, 3, ...) so that the first input value of the first input terminal 10A ( ⁱ ) and the initial input value of the second input selection terminal 10B ( multiplying ^j ) ⁱ ㆍ Multiply by outputting ^j . The circuit configuration and operation of other parts at this time are the same as those of division.

Referring to the operation of the present invention in more detail with reference to the embodiment as follows. First of all, the number of pidgets ³⁶ , the number of jets ^{If j18} , m = 8, n = 8, the number of ^pidgets as the first input ( ³⁶ enters the first input selection stage 10A and the division unit 13A is selected by the multiplication and division selection signal C of the multiplication and division selection unit 16. ^{To 36} ) ^255-8 or 1 / ^The value multiplied by ⁸ is input to the first flip flop.

At this time, the second input, that is, the number of jets applied to the second input selection terminal 10B, is selected. ¹⁸ is an element (memorized in the comparison unit 14) ⁰ to ⁷ ) are compared with the comparison unit 14. Comparator 14 ⁰ and jets ( ¹⁸ ) Exclusive Oasis, ¹ lesson ¹⁸ , Exclusive Oachi, Go On ⁷ lessons Output ¹⁸ exclusive orifices. Since there is no pattern that matches the input value, the output value of the NOR gate using the outputs of the comparator 14 as input is ＂1＂. This value enables the first flip-flop 11A and at the same time the number of jets ( ¹⁸ ) ^255-8 or 1 / Enable the second flip-flop that takes the value multiplied by ⁸ . Subsequently, the first flip flop 11A is ³⁶ / ^{When 8} is fed back to the first input selection terminal 10A, the divider 13A ³⁶ / ( ⁸ ㆍ ⁸ ) and input to the first flip-flop 11A. The second flip flop 11B is produced in the above process. ¹⁸ / ^{Feeds 8 back} to the second input selection terminal 10B. At this time, the second input selection stage is fed back value ( ¹⁰ ) Select and print. Comparing ¹⁰ again with the patterns in the comparison section, there is no matching pattern. Therefore, the first and second flip-flops 11A and 11B are enabled by the output signal of the no-gate, which has inputted the output signal of the comparator.

Then, the first flip flop 11A is again ³⁶ / ( ⁸ ㆍ ⁸ ) and at the first input selection stage 10A, ³⁶ / ( ⁸ ㆍ ⁸ ) The selected value is selected and output. At this time, in the second flip-flop 11B ¹⁰ / ^{The eighth} value is input and fed back to the second input selection stage 10B. The value selected in the second input selection terminal 10B (( ¹⁰ / ⁸ ) = ² ) again the element pattern ( ⁰ to ⁷ ). At this time, since there is a pattern corresponding to the comparator 14, the output value of the noah gate that takes the output value output from the comparator 14 as an input is 0. Thus, the first and second flip-flops 11A and 11B are disabled. In addition, the output selector 15 outputs the output value at the first input selector 10A by the output signal from the comparator 14. ³⁶ / ( ⁸ ㆍ ⁸ )) ^255-2 or 1 / ² multiplied ³⁶ / ¹⁸ is selected to output ³⁶ / ¹⁸ ). This operation also appears when multiplying, and the multiplication section 13B is selected by the multiplication selection section 16 to multiply the multiplicand. ⁹ , multiplier ^{If 18} , m = 8, and m = 8, the multiplicand (s) output from the first input selection terminal 10A ( ⁹ ) on ^The value multiplied by ⁸ ( ⁹ ㆍ ⁸ ) is input to the first flip-flop 11A. At this time, the multiplier selected by being applied to the second input selection terminal 10B ( ¹⁸ ) is compared with the elements stored in the comparator 14. Since there is no pattern to match, the no-gate output value is " 1 " to enable the first and second flip-flops 11A and 11B.

Therefore, the first flip flop 11A ⁹ ㆍ ⁸ is fed back to the first input selection terminal 10A and the second flip-flop 11B is ¹⁸ / ⁸ i.e. ¹⁰ is fed back to the second input selection terminal 10B. again ^{When 10} is compared with the elements of the comparator 14, since there is no match, the first and second flip-flops 11A and 11B are enabled. Then, the first flip flop 11A ⁹ ㆍ ⁸ ㆍ ^{The 8} value is fed back to the first input selection terminal 10A and the second flip-flop 11B is ¹⁰ / ^The value ⁸ is fed back to the second input selection terminal 10B.

Again, the value selected in the second input selection terminal 10B ( ^{When 2} ) is compared with the elements of the comparator 14, there is a matching pattern. Therefore, the output of the NOA gate becomes '0', thereby disabling the first and second flip-flops 11A and 11B. At this time, the comparator 14 outputs a control signal, and the output selector 15 multiplies the multiplication part by the signal (that is, ⁹ ㆍ ⁸ ㆍ ^{8 0} to Value of ⁷ ) ⁹ ㆍ ⁸ ㆍ ⁸ × ² One value is printed. Multiplicand ( ⁹⁾ eda multiplier ( Multiply by ¹⁸ ).

The above embodiment is a specific example, and various modifications and changes may be made without departing from the spirit and scope of the invention. In the above sense, an embodiment of a circuit corresponding to part A of FIG. 3 is illustrated in FIG. 4. This example uses an input on GF (2 ⁸ ). Multiply by ^254, that is, ^The circuit which has the result of dividing by ¹ as an output value is shown.

Such the present invention has the advantage of increasing the integration of the chip to correct the error in the circuit configuration does not use a ROM or PLA when configuring the operation circuit and the complexity of the hardware is reduced.

Claims (5)

In the arithmetic circuit on Galoache GF (2 ^m ), patterns of the output values of the first and second input selection stages 10A and 10B for selecting an input and the second input selection stage 10B and the memorized patterns are obtained. First and second flip-flops 11A and 11B and the first input selection stage 10A controlled by the comparator 14 to compare and the output signal of the logic gate which takes the output of the comparator 14 as an input. Control signal of multiplication and division selection section 16 and multiplication section 13B for selecting multiplication section 13B and division section 13A of the calculation section 13 and multiplication section 13; And an output selection section (15) for selectively outputting the calculation value selected by said multiplication and division selection section (16). 2. The arithmetic circuit according to claim 1, wherein a logic gate for outputting the control signals of the first and second flip-flops (11A, 11B) is constituted by a noah gate. 2. The galo according to claim 1, wherein the multiplication and division selecting section (16) selects the multiplication section (13B) and division section (13A) of the calculation section (13) by the multiplication and division selection signal (C). Arithmetic circuit on Aceh. 2. The arithmetic circuit according to claim 1, wherein the first and second input selection stages (10A, 10B) and the multiplication and division selection unit (16) comprise a multiplexer. The method of claim 1, wherein the comparison unit 14 comprises an exclusive oragate having a pattern of the element selected in the second input selection stage 10B as a type force as a pattern of the elements stored in memory as one input. Computation circuit on Galoache.