KR930010109B1

KR930010109B1 - Method of forming isolation area

Info

Publication number: KR930010109B1
Application number: KR1019910007581A
Authority: KR
Inventors: 나관구
Original assignee: 금성일렉트론 주식회사; 문정환
Priority date: 1991-05-10
Filing date: 1991-05-10
Publication date: 1993-10-14

Abstract

The method for forming an isolation region of a semiconductor device comprises (a) forming a buffer oxide film (2), a first nitride film (3) and a CVD oxide film (4) on the substrate (1) in order, (b) selectively photoetching the films (2,3,4) to form an active region pattern, (c) covering a first SOG (5) on the whole surface, and etching back it to form a first SOG side wall (5) on the side surface of the pattern, (d) forming a second nitride film (6) on the whole surface, and covering a second SOG (7) on the film (6), (e) anisotropy etching the film (6) and the SOG (7) to define an isolation region (10), (f) removing the residual SOG (7), and implanting a field ion, (g) removing the film (4), (h) forming a field oxide film (8) on the region (10), and (i) removing the SOG (5) and the films (3,6).

Description

Method of forming an isolation region of a semiconductor device

제 1 도는 종래의 반도체 소자 격리영역 형성공정 단면도.1 is a cross-sectional view of a conventional semiconductor device isolation region forming process.

제 2 도는 본 발명의 반도체 소자 격리영역 형성공정 단면도.2 is a cross-sectional view of a semiconductor device isolation region forming process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 버퍼산화막1 substrate 2 buffer oxide film

3 : 제 1 질화막 4 : CVD산화막3: first nitride film 4: CVD oxide film

5 : 제 1 SOG 6 : 제 2 질화막5: first SOG 6: second nitride film

7 : 제 2 SOG 8 : 필드산화막7: second SOG 8: field oxide film

본 발명은 반도체 소자의 격리영역 형성방법에 관한 것으로, 특히 서브-마이크로급 디바이스 제조에 적당하도록 한 격리공정에 있어서, 격리영역을 축소시켜 소자의 고집적화를 이룰 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an isolation region of a semiconductor device. In particular, in an isolation process suitable for manufacturing a sub-micro device, the isolation region is reduced to achieve high integration of the device.

종래 반도체 소자의 격리영역 형성방법은 제 1a 도와 같이 기판(10)위에 버퍼산화막(11)을 성장시키고 (b)와 같이 상기 산화막(11)위에 질화막(12)을 형성한 후 (c)와 같이 마스킹 공정에 의해 격리영역이 형성될 부분의 산화막(11)과 질화막(12)를 제거한다.In the conventional method of forming an isolation region of a semiconductor device, the buffer oxide film 11 is grown on the substrate 10 as shown in FIG. 1A and the nitride film 12 is formed on the oxide film 11 as shown in (b). The masking process removes the oxide film 11 and the nitride film 12 in the portion where the isolation region is to be formed.

그리고 (D)와 같이 필드이온주입을 실시하고 (E)와 같이 필드산화 공정에 의하여 필드산화막(13)을 형성한 후 질화막(12)을 제거한다.The field ion implantation is performed as shown in (D), and the nitride film 12 is removed after the field oxide film 13 is formed by the field oxidation process as shown in (E).

그러나, 상기와 같은 종래 방법에 있어서는 액티브영역이 격리영역으로 인하여 일정한 범위내에서 한정되는 문제가 있으며 필드산화막(8)의 세부리 형상(Bird's beak)으로 인하여 디바이스의 집적도를 향상시키기 어려울 뿐만 아니라 실리콘 에치시 실리콘이 손상되기 쉬워 누설전류가 발생하게 되는 문제가 있다.However, in the conventional method as described above, there is a problem that the active region is limited within a certain range due to the isolation region, and it is not only difficult to improve the device density due to the Bird's beak of the field oxide film 8, There is a problem that leakage current is easily generated when silicon is easily damaged.

본 발명은 이와같은 종래의 제반문제를 해결하기 위한 것으로, 격리영역을 축소시키고 액티브영역을 늘리므로 소자의 집적도를 향상시킬 수 있는 반도체 소자의 격리영역 형성방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve such a conventional problem, and an object thereof is to provide a method for forming an isolation region of a semiconductor device which can reduce the isolation region and increase the active region, thereby improving the integration of the device.

이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제 2 도에 의하여 상세히 설명하면 다음과 같다. 먼저 (a)와 같이 기판(1)위에 300-500Å 두께의 버퍼산화막(2)을 성장시키고 그 위에 LPCVD법에 의해 1000-2000Å 두께의 제 1 질화막(3)을 형성하고 그 위에 CVD방법에 의해 2500-3000Å 두께의 산화막(4)을 형성한 후, (b)와 같이 사진식각 공정에 의해 상기 산화막(4), 제 1 질화막(3), 버퍼산화막(2)을 선택적으로 식각하여 소정의 액티브영역 패턴을 형성한 다음 (c)와 같이 결과물 전면에 제 1 SOG(5)를 1000-3000Å 두께로 도포하고 에치백하여 (d)와 같이 제 1 SOG측벽(5)을 형성한다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings. First, as shown in (a), a buffer oxide film 2 having a thickness of 300-500 kPa is grown on the substrate 1, and a first nitride film 3 having a thickness of 1000-2000 kPa is formed thereon by the LPCVD method. After forming an oxide film 4 having a thickness of 2500-3000 mm 3, the oxide film 4, the first nitride film 3, and the buffer oxide film 2 are selectively etched by a photolithography process as shown in (b) to provide a predetermined active. After forming the region pattern, as shown in (c), the first SOG 5 is applied to the entire surface of the resultant with a thickness of 1000-3000 mm 3 and etched back to form the first SOG side wall 5 as shown in (d).

그리고 (e)와 같이 전표면에 제 2 질화막(6)을 LPCVD법에 의해 500-1500Å 두께로 증착하고 그 위에 (f)와 같이 제 2 SOG(7)를 1500-3000Å 두께로 도포한다. 이어서 이방성식각을 실시하여 상기 제 2 SOG(7)와 제 2 질화막(6)을 식각하여 기판의 소정부분을 노출시킴으로써 격리영역(10)을 정의한다.Then, as shown in (e), the second nitride film 6 is deposited to a thickness of 500-1500 kPa by the LPCVD method, and the second SOG 7 is coated to a thickness of 1500-3000 kPa as shown in (f) above. Next, the isolation region 10 is defined by performing anisotropic etching to etch the second SOG 7 and the second nitride film 6 to expose a predetermined portion of the substrate.

다음에 (h)와 같이 상기 제 2 SOG(7)를 제거하고 격리영역에 필드이온주입을 실시한 후 (Ⅰ)와 같이 CVD산화막(4)을 제거한다. 이어서 (j)와 같이 필드산화물 실시하여 필드산화막((8)을 형성한 후 제 1 SOG(5)와 제 1 SOG(3)(6)을 제거하면 결국(g)와 같이 축소된 격리영역을 얻을 수 있다.Next, the second SOG 7 is removed as shown in (h), and field ion implantation is performed in the isolation region, and then the CVD oxide film 4 is removed as shown in (I). Subsequently, the field oxide film (8) is formed by field oxide as shown in (j), and then the first SOG 5 and the first SOG 3 and 6 are removed. You can get it.

이상에서 설명한 바와같은 본 발명은 0.3-0.2μm급 반도체 소자의 격리영역 형성공정에 있어서 새부리 형상을 방지함과 아울러 격리영역을 종래보다정도 축소시킬 수 있어 소자의 고집적화를 이룰 수 있는 효과가 있다.As described above, the present invention prevents the beak shape in the process of forming the isolation region of a 0.3-0.2 μm-class semiconductor device, and also isolates the isolation region from the prior art. Since it can be reduced to a certain extent, there is an effect of achieving high integration of the device.

Claims

Forming a buffer oxide film (2), a first nitride film (3), and a CVD oxide film (4) on the substrate (1) in turn, and by means of a photolithography process, the CVD oxide film (4), the first nitride film (3), and a buffer. Selectively etching the oxide film 2 to form a predetermined active region pattern, applying and etching back the first SOG 5 on the entire surface of the resultant to form the first SOG side wall 5 on the active region pattern side surface. Process, forming a second nitride film 6 on the entire surface of the resultant, and applying a second SOG 7 thereon, and etching the second nitride film 6 and the second SOG 7 by anisotropic etching to isolate the region. A process of defining (10), a process of removing the remaining second SOG (7), performing a field ion implantation, a process of removing the CVD oxide film (4), a field oxidation process, and performing a field oxidation film on the isolation region (8) forming, removing the first SOG (5) and the first and second nitride film (3) (6) Isolation regions formed in a semiconductor device according to claim.