KR930006477B1 - Abnormal condition compensating method and apparatus - Google Patents

Abstract

The apparatus maintains a current mode without halting the operation of a microprocessor when a VTR is in fault. The method is composed of several stages: the 1st stage (S5) for generating interrupts in a period of certain time; the 2nd stage (S21-S23) for generating a certain signal for interruption through the output port (Pout) of a microprocessor; the 3rd stage (S6,S7) for discriminating abnormal state; the 4th stage (S8-S10) for storing the current data when in normal state; and the 5th stage (S11-S19) for replacing current data with the stored data when in abnormal state.

Description

VTR abnormal state compensation method and device

1 is a circuit diagram showing a preferred embodiment of the present invention.

2A and 2B are views for explaining the operation of the time delay circuit 80 of FIG.

3 is a flowchart schematically illustrating an operation of a conventional microcomputer.

4 is a flowchart of interrupt processing according to the present invention.

5 is a flow chart of a main routine according to the present invention.

6 is a flowchart of a reset process according to the present invention;

* Explanation of symbols for main parts of the drawings

80: time indicating circuit 90: status display circuit

100: differential circuit 110: conventional reset circuit

120: microcomputer 130: reset pulse generating circuit

AND ₁ : AND gate C ₁ , C _a : condenser

D ₁ , D ₂ : Diodes R ₁ to R ₄ , R, Rb: Resistance

The present invention relates to a VTR whose function is controlled by a micro-computer (hereinafter referred to as a 'microcom'), for maintaining the current mode without stopping the operation of the microcomputer when an abnormal state occurs due to static electricity or electric shock. A method and apparatus therefor.

In the conventional VTR, when the abnormal state caused by static electricity or electric shock occurs, the operation of the microcomputer is interrupted, and when such an event occurs, no key operation is accepted and the VTR timer display part displays a strange shape.

If such an abnormal condition occurs, it is solved by completely resetting the device after removing the power of the device completely and then resetting it by the reset circuit.However, the mode in use is completely changed and only returns to the initial state. Inconvenient to use, and most users are embarrassed or troubleshoot because they do not know how to do this.

The present invention has been devised to solve the above problems, and generates a capacitive effect and instantaneous reset signal of the capacitor to control the clock pulse generation program and the time delay to detect the abnormal state of the VTR. By using a differential circuit and a reset program for discriminating between existing resets and abnormal conditions, the purpose of the present invention is to maintain the current operation mode without interrupting the operation of the microcomputer even when an abnormal state of the VTR occurs. do.

In order to achieve the above object, the method of the present invention, which maintains data related to a predetermined mode selected when an abnormal state occurs in a VTR controlled by a microcomputer, generates an interrupt at a predetermined time interval to investigate whether an abnormal state occurs. Generating a predetermined signal indicative of the interrupt generation through a predetermined output port of the microcomputer whenever the interrupt is generated, and inputting through a predetermined input port of the microcomputer to indicate occurrence of the abnormal state. Determining whether or not the abnormal state has occurred by checking a status signal of the present state; Storing as a mecca, the current time, and the abnormal state occurs If it is determined that the current mode, the current mecha, each data value of the current time and each data value associated with the mode, mechanism, time of the current state stored in the predetermined storage place is not the same and the current mode is not the same. , The present Mecca, characterized in that it comprises a step of replacing each as the current time.

Further, in the VTR, which is reset in response to a predetermined signal provided through a reset terminal from the outside and whose overall functions are controlled by a microcomputer having at least one input port and an output port; According to another aspect of the present invention, there is provided an apparatus comprising: means for generating an interrupt for instructing to inspect an operation state at a predetermined time interval; Means for generating a predetermined first state signal indicating a normal state through the output port in response to the occurrence of the interrupt; Means for detecting whether an abnormal state occurs by examining a predetermined signal provided through the input port, and storing a current mode, a mechanism state, and a time when an abnormal state occurs; Delay means for receiving the predetermined first state signal provided from the output port of the marker and delaying the predetermined first state signal for a predetermined time; Status display means for providing, to the input port of the microcomputer, a second predetermined state signal indicative of the operational state of the microcomputer in response to the output of the delay means; And reset pulse generating means for resetting the micom by providing a predetermined pulse to the reset terminal of the micom when the second predetermined state signal provided from the state display means indicates the abnormal state. Is characteristic. The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows the configuration of a circuit according to a preferred embodiment of the present invention. Looking at the configuration, a time delay comprising a resistor R ₁ and a capacitor C _{2 at} an output terminal Pout of the microcomputer 120 is shown. A circuit 80, and each base of two transistors TR ₁ and TR ₂ constituting the status display circuit 90 is connected to an output terminal of the time delay circuit 80, and the transistor TR _While the emitter of ₁ ) is grounded, the collector is connected to the power supply terminal A ⁺ through the resistor R ₂ and connected to the input terminal Pin of the microcomputer 120 through the diode D ₁ . The transistor TR ₂ is connected to the input terminal Pin of the microcomputer 120 through the diode D ₂ while the collector is grounded and the emitter is connected to the power supply terminal A ⁺ through the resistor R ₃ . do. In addition, a reset pulse generator circuit 130 is connected between the output terminal of the state display circuit 90 and the reset terminal Reset of the microcomputer 120. The reset pulse generating circuit 130 has a differential circuit 100 connected to the output terminal of the status display circuit 90, a base is connected to the differential circuit 100, the emitter is grounded, and the collector is a resistor (R _4). ) And a transistor TR ₃ connected to a power supply terminal B ⁺ , an output terminal of the existing reset circuit 110 and a collector of the transistor TR ₃ , respectively, and two input terminals are respectively connected, and the output terminal is the microcomputer ( And an AND gate AND ₁ connected to the reset terminal Reset of 120.

In addition, the microcomputer 120 according to the present invention has a first function realization means 121 for generating an interrupt signal (interruptsignal) instructing to check the operation state at a predetermined time interval, and in response to the interrupt signal The second function realization means 122 for generating a status signal indicating a normal state through the output port Pout and a predetermined signal provided to its input port P _IN to detect whether an abnormal state has occurred. And a third function realization means 123 for storing a current operation mode, a mechanism state, and a time when an abnormal state occurs.

The operation of the present embodiment having the above configuration will now be described in detail with reference to the accompanying drawings.

3 is a view briefly illustrating a process in which the microcomputer 120 performs a control operation in a typical VTR. When power is supplied to the VTR by turning on the switch, the microcomputer 120 is initialized to the predetermined mode by the reset circuit 110 (S1). The microcomputer 120 initialized as described above sequentially checks (S ₂ ) a plurality of input ports (not shown) connected to keys (or function buttons) to investigate what functions the user wants and selects the user. In order to perform a control corresponding to a function, a main program stored in an internal ROM (not illustrated) is performed (S ₃ ). When the microcomputer 120 performs the main program according to the user's function selection, for example, when a change in the function mode occurs (that is, when the user changes to another mode from the current function mode of the user), the operation of the microcomputer 120 is performed. The interrupt is interrupted and the function of the current mode is stopped (S ₄ ).

4 through 6 illustrate flowcharts for explaining a function of a microcomputer further included according to the present invention in FIG. 3 showing a conventional microcomputer function performing process. First of all, FIG. 4 shows the interrupt generating function S ₅ added to the existing interrupt generation in the interrupt routine S ₄ of FIG.

In the present invention, as shown in FIG. 4, an interrupt is generated at a predetermined time interval (for example, the pulse period of the output port Pout of the microcomputer 120), so that the investigation of the occurrence of the abnormal state is performed. If it is found to have occurred, compensate for it.

Therefore, the interrupt routine acts as a means of providing an opportunity to investigate whether the microcomputer 120 itself has generated an abnormal state by interrupting the operation of the microcomputer 120 at predetermined time intervals. That is, the interrupt routine provides a function realization means for instructing the microcomputer 120 to investigate whether an abnormal state has occurred.

5 is interrupted by an interrupt routine (see FIG. 4), the microcomputer 120 detects whether an abnormal state has occurred prior to execution of the conventional main program, and compensates for the abnormal state when the abnormal state occurs. It shows the operation performed to make it, the mode compensation processing is performed prior to the execution of the conventional main program.

Finally, FIG. 6 illustrates a process in which a reset operation of the microcomputer 120 is performed according to the present invention. In accordance with this routine, the microcomputer 120 determines whether an interrupt is generated by an interrupt routine (see FIG. 4). If it is determined (S ₂₁ ) that the result is that an interrupt has occurred (YES in step S ₂₁ ), then a low-level signal is output from the output terminal Pout of itself 120 (S ₂₂ ). If it is determined that no is generated (NO in step S ₂₁ ), a high level signal is output from its output terminal Pout (S ₂₃ ).

Therefore, in the present invention, since the interrupt is generated at a predetermined time interval by the interrupt routine of FIG. 4, a square wave or pulse of a predetermined frequency is generated from the output port Pout of the microcomputer 120 in the normal state. (Steps S ₂₁ to S ₂₃ ).

Such pulse generating steps S ₂₁ to S ₂₃ function as means for generating a status signal indicating whether the microcomputer 120 is in a normal state or an abnormal state. That is, the reset routine of FIG. 6 provides a status display function to the microcomputer 120.

However, when an abnormal state occurs, the potential level of the signal output through the output port Pout of the microcomputer 120 is fixed to low or high. In FIG. 1, in a steady state, a pulse of a predetermined frequency is generated at the output terminal Rout of the microcomputer 120. At this time, the period of the pulse output from the output terminal (Rout) is smaller than the time constant by the resistance (R ₁ ) and the capacitor (C ₁ ) of the time delay circuit (80).

Therefore, in the steady state, the time delay circuit 80 acts as an integrating circuit and its output becomes a value of V _pout / 2 (V). Here, V _pout represents the high level potential of the output terminal Pout of the microcomputer 120. In the steady state, since the output of the time delay circuit 80 is V _pout / 2, the two transistors TR ₁ and TR _{2 in the} state display circuit 90 are turned on.

Therefore, the output of the status display circuit 90 goes low. Since the output potential of the status display circuit 90 becomes OV, the output potential of the differential circuit 100 in the reset pulse generating circuit 130 also becomes low level. As a result, the transistor TR ₃ is turned off and the potential of the collector becomes high level.

Therefore, in the steady state, the output level of the AND gate AND ₁ (or the output of the reset pulse generation circuit 130) is determined by the output level of the reset circuit 110. The reset circuit 110 operates only when power is first supplied to the VTR through a plug to initialize the microcomputer 120. When the abnormal state occurs, the reset circuit 110 does not perform the reset function. The reset circuit 110 outputs a low level signal when performing the reset function, and outputs a high level signal when not performing the reset function.

Therefore, in the normal state, since the output of the AND gate AND ₁ is at the high level, the microcomputer 120 does not enter the reset state.

As described above, in the present invention, in order to check whether an abnormal state occurs, a pulse of a predetermined frequency is generated from the output terminal Pout of the microcomputer 120 and an abnormal state every predetermined period of the pulse. Examine (detect) whether or not

A method of detecting the occurrence of such an abnormal state will be described in detail with reference to FIG. 5 as follows. When an interrupt is generated at a predetermined time interval by the interrupt routine (see FIG. 4), the microcomputer 120 reads the data signal input to its input terminal P _IN (S ₆ ).

As described above with reference to FIG. 6, in a steady state, a pulse of a predetermined frequency is generated from the output terminal Pout of the microcomputer 120, but in an abnormal state, the potential of the output terminal Pout is high. It is fixed to the potential of either the level potential B ⁺ V or the low level potential OV.

Therefore, the microcomputer 120 checks whether the potential of the input port P _IN is at a high level in order to detect whether an abnormal state has occurred (S ₇ ). If the potential of the data signal input through the input port P _IN is at a high level, it indicates that an abnormal state has occurred.

The reason for this will now be explained with reference to FIG. When an abnormal state occurs and the potential of the output terminal Pout of the microcomputer 120 is fixed at a high level, the output signal of the time delay circuit 80 has a waveform delayed by a predetermined time ΔT ₁ as shown in FIG. 2C. . The reason why such a time delay circuit 80 is configured will be described later in detail. When the high level signal delayed by the time delay circuit 80 by a predetermined time ΔT ₁ is provided to the status display circuit 90, the first transistor TR ₁ is in an operating state and the second transistor TR ₂ is negative. It becomes an operation state. Therefore, the output signal of the status display circuit 90 has a high level potential. When an abnormal state occurs, when the signal output through the output terminal Pout of the microcomputer 120 is fixed at the low level, the transistor TR ₁ of the state display circuit 90 becomes inoperative and the other transistor TR ₂ ) becomes an operation state, and even in this case, the output signal of the state display circuit 90 has a high level potential.

As can be seen from the above, even if an abnormal state is generated by electrostatic or electrical shock, the output terminal Pout of the microcomputer 120 is fixed to either the high level or the low level potential. The output of has a high level potential. In other words, when an abnormal condition occurs, the output of the status display circuit 90 is always at a high level. Therefore, returning to the description of step S ₇ of FIG. 5, the microcomputer 120 can determine whether an abnormal state has occurred by examining the potential of the data signal received through its input port P _IN . . That is, in step S _7, if the input port (P _IN) is at a high level electric potential of the microcomputer 120 is detected, and ha level that the abnormality has occurred or is detected to be the steady state. Stored in the normal when the state that detected (i.e., if NO in step S _7), a given memory location having a variable name of the mode data indicating the state of the ongoing mode, the current mode (NOWMODE) '(or a kind of a register) (S ₈ ).

In addition, the data indicating the mechanism currently being controlled is recorded in the 'NOWMECHA' variable, and the state of the timer currently being operated is stored in the 'NOWTIME' (S ₉ and S ₁₀ ). Step is NO in S ₇ (i.e., an abnormal state occurs under two is detected), the abnormal state mode and the mechanism and the timer current mode of the status of the current mechanism, at least not the same, the current comparison time and each By replacing the current data with the data of the state, even if the microcomputer 120 is reset due to the occurrence of the abnormal state, the mode, mechanism, and time data of the abnormal state can be maintained as it is (S ₁₁ to S ₂₀ ). Referring to FIG. 5, comparison 1 (step S ₁₂ ) compares current mode data stored in a normal operation state with mode data in an abnormal state, and comparison 2 (step S ₁₅ ) is performed in a normal operation state. Comparing whether the data related to the currently operating mechanism is the same as the mechanism data at the time of occurrence of an abnormal state, comparison 3 (step S ₁₈ ) compares whether the current time data at the steady state and the time data at the time of an abnormal state are the same. Step.

As described above, the microcomputer 120 is reset by the existing reset circuit 110 at the time of initial power input, and the predetermined clock is reset in the reset program as shown in the flowchart shown in FIG. By setting a status display means (S21 to S23 in FIG. 6) indicating whether an abnormal state or a normal state is generated so that a clock pulse indicating the state of the microcomputer 120 is output to the microcomputer 120 output terminal Pout. do.

The clock signal is applied to the base of the transistors TR ₁ and TR ₂ through the resistor R ₁ and the capacitor C ₁ and is applied to the DC voltage of V _pout / 2 [V]. ₁ and TR ₂ are all in operation.

On the other hand, in the case where an abnormal state occurs and the output of the delay circuit 80 becomes either of high or low level, only the transistor TR ₁ is operated at a high level, and at low level, the transistor TR _2. ) Is in the operating state.

As described above, when an abnormal state occurs and any one of the transistors TR ₁ and TR ₂ is operated, a high level signal is transmitted through the diode D ₁ and D ₂ to the differential circuit 100 and the microcomputer ( 120 is applied to the input terminal P _IN . At this time, the high-level signal passing through the differential circuit 100 is converted into a sawtooth waveform trigger pulse and applied to the base of the transistor TR ₃ . Accordingly, the transistor TR ₃ is momentarily in an operating state, and thus the collector has a low level potential. As a result, a low level signal is applied to one terminal of the AND gate AND ₁ , which is a logic means, and the output of the AND gate AND ₁ is maintained at a low level regardless of the output signal of the existing reset circuit 110. Done. Therefore, when an abnormal state occurs, a low level signal is instantaneously applied from the AND gate AND ₁ to the reset terminal Reset of the microcomputer 120 and the microcomputer 120 is reset. In response to a signal applied to the input terminal P _{IN of} the microcomputer 120, the microcomputer 120 performs an existing reset program as shown in the operation flowchart of FIG. 6.

On the other hand, in FIG. 1, a transistor (TR ₁₎ (TR ₂₎ when so provided is the power directly to the power supply terminal (A ⁺⁾ is connected to the collector power up time of preparation initial voltage of the transistor is (TR ₁₎ (TR ₂₎ Before the output signal of a predetermined level is applied from the output terminal Pout of the microcomputer 120 to the base of the transistor, a negative state voltage of high or low is applied to the base of the transistor TR ₁ (TR ₂ ). One transistor is in an operating state, and a high signal is applied to the input terminal P _IN of the microcomputer 120.

Therefore, the contradiction of performing the reset program in the abnormal state without performing the existing reset program according to the operation flow diagram of FIG. 4 occurs, thus resetting the power source A ⁺ as shown in FIG. If the power delayed by the capacitor Ca rather than the time ΔT ₂ and delayed by the time ΔT ₁ is supplied to the first diagram, the power supply during the reset time ΔT ₂ due to the initial power-on is turned on. Since A ⁺ ) is low, a low signal is input to the input of the microcomputer P _IN to perform the existing reset program of FIG. 6.

As described above through the preferred embodiment, the reset signal is generated when the power is turned on for the first time, and the reset signal is applied to the microcomputer. However, when the abnormal state occurs, it is troublesome to remove the power and then turn it on again. Since the previous mode is not executed and consumers are not aware of this fact, the demand for after-sales service of the device is high. However, the present invention detects when an abnormal condition occurs and generates a reset signal. The advantage is that the mode continues.

Claims (6)

A method of maintaining data related to a predetermined mode selected when an abnormal state occurs in a VTR controlled by the microcomputer 120, wherein the execution of the selected general function mode is performed, wherein a predetermined time interval is examined to investigate whether the abnormal state occurs. Generating an interrupt (S ₅ ), and generating a predetermined signal indicating the interrupt generation through a predetermined output port (Pout) of the microcomputer 120 whenever the interrupt is generated (S ₂₁ to S _23). And a predetermined state signal input through a predetermined input port (P _IN ) of the microcomputer 120 to determine whether the abnormal state has occurred (S ₆ , S). ₇ ) And if it is determined that the abnormal state has not occurred, the data corresponding to the mode, mechanism, and time of the current state in the predetermined storage location is changed to the current mode, the current mechanism, and the current time. Document storing each (S ₈ ~ S ₁₀₎ and, if it is determined that the abnormality has occurred is stored in the predetermined storage place for the current mode, the current mechanical, and the current status mode for each data value of the current time And comparing each data value with respect to the mechanism, time, and replacing each of the current mode, the current mechanism, and the current time (S ₁₁ to S ₁₉ ). Compensation Method. The method of claim 1, wherein the determining whether the abnormal state occurs comprises determining that the predetermined state signal input through the predetermined input port P _IN is a normal state if the predetermined state signal is not a predetermined level. An abnormal state compensation method for a VTR, characterized by determining that an abnormal state has occurred. The abnormal state compensation method of a VTR according to claim 1, wherein the step of generating the interrupt generates a square wave of a predetermined frequency through the predetermined output port (Pout) of the microcomputer (120). All functions are reset by the microcomputer 120 which is reset in response to a predetermined signal provided through a reset terminal from the outside and has at least one input port (P _IN ), an output port, and (Pout). In the controlled VTR; The microcomputer 120 generates means 121 for instructing to check the operation state at predetermined time intervals and a predetermined state indicating that the microcomputer 120 is in a normal state through the output port Pout in response to the occurrence of the interrupt. Means 122 for generating a first state signal of the signal and a predetermined signal provided through the input port P _IN to detect whether an abnormal state has occurred, and when an abnormal state occurs, the current mode and mechanism state and Means 123 for storing time; Delay means (80) for receiving the predetermined first state signal provided from the output port (Pout) of the microcomputer (120) and delaying the predetermined first state signal for a predetermined time; Status display means (90) for providing a predetermined second state signal indicating the operating state of the microcomputer (120) to the input port (P _IN ) of the microcomputer (120) in response to the output of the delay means (80). ) And; When the predetermined second state signal provided from the state display means 90 indicates the abnormal state, the microcomputer 120 provides a predetermined pulse to the reset terminal of the microcomputer 120. The abnormal state compensation device of the VTR, characterized in that it comprises a reset pulse generating means for resetting the. 5. The apparatus of claim 4, wherein the state display means (90) comprises two transistors (TR ₁ , TR ₂ ) operated in different forms, and the two when the output of the delay means (80) is high or low. An abnormal state compensation device for a VTR, wherein only one of the transistors TR ₁ and TR ₂ operates. 5. The reset pulse generating means (130) according to claim 4, wherein the reset pulse generating means (130) receives the output of the status display means (90) and differentiates the time so that the operation is performed by the output of the differential means (100) and the differential means (100). A logic gate provided to a reset terminal (Reset) of the microcomputer 120 by performing a logical operation on the controlled transistor TR ₃ , the output signal of the transistor TR ^× , and the output signal of the existing reset means 110. An apparatus for compensating for an abnormal state of a VTR, comprising means.

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