JPS6138363Y2 - - Google Patents

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Publication number
JPS6138363Y2
JPS6138363Y2 JP13623779U JP13623779U JPS6138363Y2 JP S6138363 Y2 JPS6138363 Y2 JP S6138363Y2 JP 13623779 U JP13623779 U JP 13623779U JP 13623779 U JP13623779 U JP 13623779U JP S6138363 Y2 JPS6138363 Y2 JP S6138363Y2
Authority
JP
Japan
Prior art keywords
output
circuit
power supply
voltage
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13623779U
Other languages
Japanese (ja)
Other versions
JPS5654841U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13623779U priority Critical patent/JPS6138363Y2/ja
Publication of JPS5654841U publication Critical patent/JPS5654841U/ja
Application granted granted Critical
Publication of JPS6138363Y2 publication Critical patent/JPS6138363Y2/ja
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は保護継電装置等の制御電源の点検回路
に関する。
[Detailed Description of the Invention] The present invention relates to an inspection circuit for a control power source such as a protective relay device.

一般に保護継電装置の中でトランジスタやIC
等を用いたいわゆる静止形継電器により構成され
た装置では、電源投入時や電源瞬断時に誤まつた
出力を出さないようにするため、一定時間出力を
ロツクするいわゆる電源異常時ロツク回路(以下
PAL回路と略す)が必要がある。このPAL回路
は、正常時(電源が確立している時)には待機状
態にあり、電源瞬断時により静止形継電器が正常
に応動しえない電圧状態になつた場合は速やかに
動作してこの静止形継電器の出力やロジツクシー
ケンス回路出力をロツクしなければならない。
PAL回路はこの点を十分に考慮して作られてい
る。ところが、このPAL回路自体に何らかの異
常が発生して正規の動作が期待しえなくなつた場
合にはこれを検出して処理しなければならない。
In general, transistors and ICs are used in protective relay devices.
In order to prevent erroneous output from being output when the power is turned on or when the power is momentarily interrupted, devices configured with so-called static relays, such as the
(abbreviated as PAL circuit) is required. This PAL circuit is in a standby state under normal conditions (when the power supply is established), and immediately operates when the static relay becomes unable to respond normally due to a momentary power interruption. The output of this static relay and the output of the logic sequence circuit must be locked.
PAL circuits are designed with this point in mind. However, if some abnormality occurs in the PAL circuit itself and normal operation cannot be expected, this must be detected and dealt with.

この検出方法として従来はミスロツク(電源正
常であるにもかかわらず静止形継電器の出力をロ
ツクしてしまう)がないかどうかを常時監視する
ことにより見付けているのみで電源異常時に正常
に動作できるか否かの確認はなされていなかつ
た。
The conventional method for detecting this has been to constantly monitor whether or not there is a mislock (locking the output of a static relay even when the power supply is normal). There was no confirmation as to whether this was the case.

本考案はこの点に鑑みなされたもので、PAL
回路が電源瞬断等の異常時に性能を発揮しうるか
どうかを点検により周期的あるいは任意の時に確
認できるようにした制御電源の常時監視及び点検
装置を提供することを目的とするものである。
This invention was devised in view of this point, and PAL
It is an object of the present invention to provide a constant monitoring and inspection device for a controlled power source, which allows checking periodically or at any time to check whether a circuit can exhibit its performance in the event of an abnormality such as a momentary power interruption.

第1図は本考案によるPAL回路の一実施例を
示す図である。図において、A,B,Cはそれぞ
れ例えば24〔V〕,12〔V〕および0〔V〕の電
圧を有する制御電源母線である。これらA−C母
線間、B−C母線間に保護装置あるいは制御装置
1を接続する。そして、前記A,B母線と直列に
それぞれ接点2A,2Bを介して電圧レベル検出
要素3A,3Bを接続する。前記接点2A,2B
は制御母線の点検時動作する図示しない補助継電
機の常閉接点である。又前記電圧レベル検出要素
3A,3Bは例れば第2図のように構成され、前
記A−C母線間に抵抗31、ツエナーダイオード
32の直列回路、抵抗33およびトランジスタ3
4の直列回路を接続し、このトランジスタ33の
ベースを前記抵抗とツエナーダイオード32の接
続点に接続しこの抵抗33とトランジスタ34と
の接続点を反転回路を構成するトランジスタ35
のベースに接続したものである。36は抵抗、3
7は出力端子、DはA,Bから独立した母線であ
る。そしてツエナーダイオード32のツエナー電
圧は例えば定格電圧の80%以上に選定されてい
る。従つて電源電圧VACが定格電圧の80%以上
の電圧であれば、ツエナーダイオードは導通し、
トランジスタ34はオフ、トランジスタ35はオ
ンになり出力端子37からは“0”信号が出力さ
れる。尚、電圧レベル検出要素3Bについても同
様に構成されている。4はオア回路であり、前記
電圧レベル検出要素3A,3Bの出力を導入し、
いずれかが“1”信号になると出力“1”を生じ
る。このオア回路4に出力が生じると引延し回路
5より、暫時保護あるいは制御装置1の出力を無
効とするようなロツク信号及び表示信号6を出力
する。7はアンド回路であり、電圧レベル検出回
路3A,3Bがともに出力“1”のとき、出力8
を生じる。
FIG. 1 is a diagram showing an embodiment of a PAL circuit according to the present invention. In the figure, A, B, and C are control power supply buses having voltages of, for example, 24 [V], 12 [V], and 0 [V], respectively. A protection device or a control device 1 is connected between these A-C busbars and between B-C busbars. Then, voltage level detection elements 3A and 3B are connected in series with the A and B buses through contacts 2A and 2B, respectively. The contacts 2A, 2B
is a normally closed contact of an auxiliary relay (not shown) that operates when inspecting the control bus. Further, the voltage level detection elements 3A and 3B are configured as shown in FIG.
4 are connected in series, the base of this transistor 33 is connected to the connection point between the resistor 33 and the Zener diode 32, and the connection point between this resistor 33 and the transistor 34 is connected to a transistor 35 constituting an inverting circuit.
It is connected to the base of 36 is resistance, 3
7 is an output terminal, and D is a bus bar independent from A and B. The Zener voltage of the Zener diode 32 is selected to be, for example, 80% or more of the rated voltage. Therefore, if the power supply voltage VAC is 80% or more of the rated voltage, the Zener diode will conduct.
The transistor 34 is turned off, the transistor 35 is turned on, and the output terminal 37 outputs a "0" signal. Note that the voltage level detection element 3B is also configured in the same manner. 4 is an OR circuit into which the outputs of the voltage level detection elements 3A and 3B are introduced;
When either becomes a "1" signal, an output "1" is produced. When an output is generated in the OR circuit 4, the extension circuit 5 outputs a lock signal and display signal 6 for temporarily protecting or invalidating the output of the control device 1. 7 is an AND circuit, and when the voltage level detection circuits 3A and 3B both output "1", the output 8
occurs.

今第1図、第2図の回路において、母線Aの電
圧が予定値よりも低下したとすると、電圧レベル
検出要素3Aが動作して信号“1”を出力し、オ
ア回路4、引延し回路5を経てロツク及び表示信
号6が出力される。この出力信号6によつて母線
AあるいはBの電圧が予定値以上降下したことが
認識できる。母線Bの電圧が予定値よりも低下し
たときも同様である。表示信号及びロツク信号6
が出力されても電圧低下した母線はAかBかの区
別はできないが、保護及び制御装置1は同時に
A,B母線から電圧をとり入れているので、いず
れか一方の電圧が低下しても出力は信頼できな
い。従つていずれかの母線電圧が低下したという
ことの表示と保護及び制御装置の出力ロツクとい
う対策で十分である。
Now, in the circuits shown in FIGS. 1 and 2, if the voltage on the bus A falls below the expected value, the voltage level detection element 3A operates and outputs a signal "1", and the OR circuit 4 A lock and display signal 6 is output via circuit 5. From this output signal 6, it can be recognized that the voltage on bus A or B has dropped by more than a predetermined value. The same applies when the voltage of the bus line B falls below the expected value. Display signal and lock signal 6
Even if is output, it is not possible to distinguish whether the voltage has dropped on the bus A or B, but the protection and control device 1 is simultaneously taking in voltage from the A and B buses, so even if the voltage on either one drops, it will not output. cannot be trusted. Therefore, it is sufficient to take measures such as displaying that the voltage of one of the busbars has dropped, protection, and locking the output of the control device.

次にPAL回路が正常であるか否かを点検する
ために、点検指令を与えて接点2A,2Bを開放
する。するとトランジスタ35のベース電流が断
たれるから、トランジスタ35はオフし、出力端
子37から“1”なる出力を生じ、電圧レベル検
出要素3A,3Bから“1”なる出力が発生す
る。この結果出力信号6が生ずるのはもとより、
アンド回路7から出力信号8が生じ、この出力信
号8の発生によつてPAL回路が正常であること
の確認ができる。
Next, in order to check whether the PAL circuit is normal or not, a check command is given to open the contacts 2A and 2B. Then, since the base current of the transistor 35 is cut off, the transistor 35 is turned off, an output of "1" is generated from the output terminal 37, and an output of "1" is generated from the voltage level detection elements 3A and 3B. As a result, not only the output signal 6 is generated, but also the output signal 6 is generated.
An output signal 8 is generated from the AND circuit 7, and by the generation of this output signal 8, it can be confirmed that the PAL circuit is normal.

第3図は本考案の別の実施例を示す図である。
点検指令により動作する切替接点2A,2Bの常
閉接点は電源A,Bと電圧レベル検出要素1A,
1Bを接続しており常開接点は抵抗RA1,RA2
たはRB1,RB2により分圧された電圧レベル検出
要素3A,3Bが動作可能な電圧を導入するので
点検指令により2A,2Bが動作すると電圧レベ
ル検出要素3A,3Bは電圧低下を検出し第1図
の場合と同様な方法でPAL回路が正常に応動で
きることの確認が行える。第3図では適当な電圧
低下模擬を抵抗分圧による方法で説明したがツエ
ナーダイオード等による方法で行つてもいつこう
にかまわない。
FIG. 3 is a diagram showing another embodiment of the present invention.
The normally closed contacts of the switching contacts 2A and 2B that operate according to the inspection command are connected to the power supplies A and B and the voltage level detection element 1A,
1B is connected, and the normally open contact introduces a voltage that can operate voltage level detection elements 3A and 3B divided by resistors R A1 and R A2 or R B1 and R B2 , so 2A and 2B are connected by inspection command. When activated, the voltage level detection elements 3A and 3B detect a voltage drop, and it can be confirmed in the same manner as in FIG. 1 that the PAL circuit can respond normally. In FIG. 3, an appropriate voltage drop simulation was explained using a method using resistance voltage division, but it does not matter at any time that it may be performed using a method using a Zener diode or the like.

第1図ないし第3図の場合電圧レベル検出要素
は電圧低下についてのみ検出可能としたが、第4
図のように構成することによつて、電圧低下は勿
論電圧上昇についても容易に点検可能である。
In the case of Figures 1 to 3, the voltage level detection element was able to detect only voltage drops, but in the case of Figure 4,
By configuring as shown in the figure, it is possible to easily check not only voltage drops but also voltage increases.

第4図において、91は抵抗、92はツエナー
ダイオード、93は抵抗、94はトランジスタ、
95はオア回路である。ツエナーダイオード92
は定格電圧の110〔%〕以上で導通し、それより
も低いときは非導通である。
In FIG. 4, 91 is a resistor, 92 is a Zener diode, 93 is a resistor, 94 is a transistor,
95 is an OR circuit. zener diode 92
is conductive when the voltage is 110% or more of the rated voltage, and non-conductive when it is lower than that.

第5図は異なる電源を容易に持ち込み得る場合
について示している。点検用の切替接点2A,2
Bの常開接点によりレベル検出要素9A,9Bの
過電圧検出レベルより高い電圧をもつ電源A′,
B′へ切替えれば各レベル検出要素9A,9Bは動
作することができ、第2図と同様の方法で確認可
能となる。また異なる電源が容易に使用しえない
場合は第6図に示すように点検指令10A,10
Bによりレベル検出要素9A,9Bを制御して通
常の検出レベルよりも強制的に下げて正常な電源
A,Bに接続された状態で動作可能にする方法で
ある。
FIG. 5 shows a case where different power sources can be easily brought in. Switching contact 2A, 2 for inspection
Power supply A', which has a voltage higher than the overvoltage detection level of level detection elements 9A and 9B due to the normally open contact of B
When switched to B', each level detection element 9A, 9B can operate, and confirmation can be made in the same manner as in FIG. In addition, if a different power source cannot be easily used, check commands 10A and 10 as shown in Figure 6.
In this method, the level detecting elements 9A and 9B are controlled by B to forcibly lower the detection level than the normal detection level to enable operation while connected to normal power supplies A and B.

以上述べたごとく本考案によれば電源が異常時
に誤出力を出す可能性がある継電器出力やロジツ
ク回路出力を押さえる機能が発揮できるか否かを
自動的に検出できる装置を提供しうるものであり
装置の信頼性を高めることに寄与するものであ
る。
As described above, according to the present invention, it is possible to provide a device that can automatically detect whether or not the function of suppressing the output of a relay or the output of a logic circuit, which may produce an erroneous output when the power supply is abnormal, can be performed. This contributes to increasing the reliability of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本案の電源異常検出回路のブロツク回
路図、第2図は電圧レベル検出要素の一例を示す
回路図、第3図、第5図および第6図は別の実施
例を示す回路図、第4図は他の電圧レベル検出要
素の例を示す図である。 A,B,C:互いに独立な電源母線、3A,3
B,9A,9B:電圧レベル検出要素、4:OR
回路、5:引延し回路、7:AND回路。
Fig. 1 is a block circuit diagram of the power supply abnormality detection circuit of the present invention, Fig. 2 is a circuit diagram showing an example of a voltage level detection element, and Figs. 3, 5, and 6 are circuit diagrams showing other embodiments. , FIG. 4 is a diagram showing an example of another voltage level detection element. A, B, C: mutually independent power bus, 3A, 3
B, 9A, 9B: Voltage level detection element, 4: OR
Circuit, 5: Extension circuit, 7: AND circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の制御用電源を必要とする保護あるいは制
御装置の電源を点検するものにおいて、複数の制
御母線それぞれに直列に接続され点検指令に応じ
て切換えられる接点と、これら接点を介してそれ
ぞれ前記制御母線に接続され、制御電源電圧が予
定値から低下あるいは上昇すると動作して出力を
生じる電圧レベル検出要素と、これら複数の電圧
レベル検出要素のいずれか1個が出力を生じる
と、前記保護あるいは制御装置の出力をロツクす
るための出力及び表示出力を生じる回路と、点検
時、前記複数の電圧レベル検出が全て動作したこ
とを検出して点検確認信号を出力する回路とから
なる制御電源の常時監視及び点検装置。
In equipment that inspects the power supply of protection or control equipment that requires multiple control power supplies, there are contacts that are connected in series to each of the plurality of control buses and are switched in response to an inspection command, and each of the control buses is connected to each of the control buses through these contacts. a voltage level detection element that is connected to the control power supply voltage and operates to generate an output when the control power supply voltage decreases or increases from a predetermined value, and when any one of the plurality of voltage level detection elements generates an output, the protection or control device A circuit for constantly monitoring and displaying a control power supply, comprising a circuit that generates an output and a display output to lock the output of the power supply, and a circuit that detects that all of the plurality of voltage level detectors are activated during inspection and outputs an inspection confirmation signal. Inspection equipment.
JP13623779U 1979-10-03 1979-10-03 Expired JPS6138363Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13623779U JPS6138363Y2 (en) 1979-10-03 1979-10-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13623779U JPS6138363Y2 (en) 1979-10-03 1979-10-03

Publications (2)

Publication Number Publication Date
JPS5654841U JPS5654841U (en) 1981-05-13
JPS6138363Y2 true JPS6138363Y2 (en) 1986-11-06

Family

ID=29367746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13623779U Expired JPS6138363Y2 (en) 1979-10-03 1979-10-03

Country Status (1)

Country Link
JP (1) JPS6138363Y2 (en)

Also Published As

Publication number Publication date
JPS5654841U (en) 1981-05-13

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