KR930004901Y1 - Display stabilizing circuit when change the mode-pattern for monitor - Google Patents

Display stabilizing circuit when change the mode-pattern for monitor Download PDF

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KR930004901Y1
KR930004901Y1 KR2019880012785U KR880012785U KR930004901Y1 KR 930004901 Y1 KR930004901 Y1 KR 930004901Y1 KR 2019880012785 U KR2019880012785 U KR 2019880012785U KR 880012785 U KR880012785 U KR 880012785U KR 930004901 Y1 KR930004901 Y1 KR 930004901Y1
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terminal
flip
flop
gate
output
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KR900004053U (en
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윤주호
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주식회사 금성사
최근선
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/146—Flicker reduction circuits

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  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

내용 없음.No content.

Description

모니터의 모드/패턴 절환시 화면 안정회로Screen stability circuit during monitor mode / pattern switching

첨부한 도면은 본 고안의 화면 안정 회로도.The accompanying drawings are screen stability circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 절환신호발생부 2 : 아날로그 스위치부1: switching signal generator 2: analog switch

B1 +: 제1전원 B2 +: 제2전원B 1 + : first power source B 2 + : second power source

Vcc : 전원단자 I1, I2: 인버터(Inverter)Vcc: Power Terminal I 1 , I 2 : Inverter

VI : 수직동기신호입력단자 AND1: 앤드게이트VI: Vertical synchronization signal input terminal AND 1 : AND gate

FF1-FF4: 플립플롭 OR1: 오아게이트FF 1 -FF 4 : Flip-flop OR 1 : Oagate

CK1-CK4: 클럭단자 RS1-RS4: 리세트단자CK 1 -CK 4 : Clock terminal RS 1 -RS 4 : Reset terminal

E : 인에이블(Enable)단자 a1, a2: 전원입력단자E: Enable terminal a 1 , a 2 : Power input terminal

본 고안은 모니터(MONITOR)의 화면 안정회로에 관한 것으로, 특히 모니터의 모드(MODE) 또는 패턴(PATTERN)을 절환할 때 발생하는 화면 불안 현상을 없앰으로써 사용자가 항상 선명한 화질의 모니터를 볼 수 있도록 한 모니터의 모드/패턴절환시 화면 안정 회로에 관한 것이다.The present invention relates to the screen stabilization circuit of the monitor (MONITOR), in particular, by eliminating the screen anxiety that occurs when switching the mode (MODE) or pattern (PATTERN) of the monitor so that the user can always see a clear picture quality monitor It relates to a screen stabilization circuit in mode / pattern switching of a monitor.

종래의 모니터에는, 모드나 패턴을 절환할 때, 순간 귀선발생 및 동기 불안 현상이 생겨 화면이 펄럭임으로써 모니터의 화질이 나빠지는 결점이 있었다.Conventional monitors have the drawback that, when switching modes or patterns, instantaneous blanking and synchronous anxiety occur and the screen flutters, resulting in poor image quality.

본 고안은 이러한 결점을 해소하기 위해 모드나 패턴 절환시에 영상신호가 화면에 디스플레이(DISPLAY)되지 않게 하여 상기의 제반 현상이 발생하지 않도록 안출한 것으로서, 이를 첨부한 도면을 참조하여 상세히 설명하면 아래와 같다.The present invention is designed to solve the above-mentioned phenomenon, so that the above-mentioned phenomenon does not occur by preventing the video signal from being displayed on the screen during mode or pattern switching, which will be described in detail with reference to the accompanying drawings. same.

첨부한 도면은 본 고안의 화면 안정화 회로도로서, 이에 도시한 바와 같이 절환신호발생부(1)의 출력신호 및 그의 반전신호가 플립플롭(FF1)(FF4)의 클럭단자(CK3)(CK4)에 각각 인가되도록 하여, 그들의 출력단자(Q3)(Q4)를 오아게이트(OR1)의 두 입력단자에 각기 접속한다. 또한 그 오아게이트(OR1)의 출력단자 및 수직 동기 신호 입력단자(VI)를 앤드게이트(AND1)의 두 입력 단자에 각각 접속하며, 그의 출력단자를 플립플롭(FF1)의 클럭단자(CK1)에 접속함과 아울러, 그 플립플롭(FF1)의 출력단자(Q1)를 플립플롭(FF2)의 클럭단자(CK2)에 접속하고, 그 플립플롭(FF2)의 출력단자(Q2)를 인버터(I2)를 통해 플립플롭(Q1-Q4)의 리세트단자(RS1-RS4)와 공통 접속한다. 그리고 상기 앤드게이트(AND1)의 일측 입력단자와 접속된 상기 오아게이트(OP1)의 출력단자를 아날로그 스위치부(2)의 인에이블단자(E)에 접속하고, 그 아날로그스위치부(2)의 전원입력단자(a1), (a2)에 제1전원(B1 +) 및 제2전원(B1 +)이 각각 인가되도록 하여 상기 아날로그스위치부(2)의 출력단자를 모니터용 CDT(Color Display Tube)의 제1전극에 접속하여 구성한 것으로, 플립플롭(FF1-FF4)의 입력단자(D1-D4)는 전원단자(Vcc)에 접속되고, 제1전원(B1 +) 전압이 제2전원(B1 +)저압보다 높으며, 상기 아날로그 스위치부(2)의 인에이블 단자(E)에 고전위, 저전위가 인가되면 그에따라 그 아날로그 스위치부(2)의 출력단자가 전원입력단자(a2), (a1)에 각각 단락되게 되어 있다.The accompanying drawings are screen stabilization circuit diagrams of the present invention, and as shown therein, the output signal of the switching signal generator 1 and the inverted signal thereof are clock terminals CK 3 (of the flip-flop FF 1 (FF 4 ) ( CK 4 ), respectively, so that their output terminals Q 3 (Q 4 ) are connected to the two input terminals of the oragate OR 1 , respectively. In addition, the output terminal of the oragate OR 1 and the vertical synchronizing signal input terminal VI are connected to the two input terminals of the AND gate AND 1 , respectively, and the output terminal thereof is the clock terminal of the flip-flop FF 1 . connected to the CK 1) also and at the same time, connected to the flip-flop (the clock terminal (CK 2) of the flip-flop (FF 2) an output terminal (Q 1) of the FF 1), and the output of the flip-flop (FF 2) The terminal Q 2 is commonly connected to the reset terminals RS 1- RS 4 of the flip-flops Q 1- Q 4 through the inverter I 2 . The output terminal of the OR gate OP 1 connected to the one input terminal of the AND gate AND 1 is connected to the enable terminal E of the analog switch unit 2, and the analog switch unit 2 CDT for monitoring the output terminal of the analog switch unit 2 by applying the first power source (B 1 + ) and the second power source (B 1 + ) to the power input terminals (a 1 ) and (a 2 ), respectively. The input terminals D 1 -D 4 of the flip-flops FF 1 -FF 4 are connected to the power supply terminal Vcc, and the first power source B 1 is connected to the first electrode of the (Color Display Tube). + ) When the voltage is higher than the second power supply B 1 + low voltage and high potential and low potential are applied to the enable terminal E of the analog switch unit 2, the output terminal of the analog switch unit 2 accordingly The self-power input terminals a 2 and a 1 are respectively shorted.

이와 같이 구성한 본 고안의 작용 및 효과를 상세히 설명하면 다음과 같다.Referring to the operation and effects of the present invention configured in this way as follows.

모니터의 모드 또는 패턴이 절환되면 절환신호발생부(1)는 그의 출력단자로 소정시간 동안만, 즉 수직동기신호 2주기 동안만 절환신호를 출력하며, 그 절환신호는 플립플롭(FF3)의 클럭단자(CK3)에 인가되는 한편, 인버터(I1)를 통해 플립플롭(FF4)의 클럭단자(CK4)에 인가되므로, 상기 절환신호가 고전위에서 저전위로, 저전위에서 고전위로 바뀔때 상기 플립를롭(FF3), (FF4)의 출력단자(Q3), (Q4)에서 각기 고전위 및 저전위, 저전위 및 고전위가 출력됨에 따라 오아게이트(OR1)의 출력신호는 고전위가 된다.When the mode or pattern of the monitor is switched, the switching signal generator 1 outputs the switching signal to only its output terminal for a predetermined time, i.e., for two periods of the vertical synchronization signal, and the switching signal of the flip-flop (FF 3 ). therefore applied to the clock terminal (CK 4) of the clock terminal flip-flop (FF 4) via the other hand, an inverter (I 1) is applied to (CK 3), wherein the switching signal over the low potential on the classical time on the low-potential change to the high potential As the high potential and low potential, the low potential and the high potential are respectively output from the output terminals Q 3 and Q 4 of the flip-flops FF 3 and FF 4 , an output signal of the OR gate OR 1 . Becomes high potential.

이때 상기 오아게이트(OR1)의 고전위 출력신호가 아날로그스위치부(2)의 인에이블 단자(E)에 인가되므로, 이 스위치부(2)의 출력단자는 전원입력단자(a2)에 단락되어 칼라 모니터용 CDT의 제1전극에 낮은 전압이 인가되며, 영상신호가 차단된다.At this time, since the high-potential output signal of the OR gate OR 1 is applied to the enable terminal E of the analog switch unit 2, the output terminal of the switch unit 2 is short-circuited to the power input terminal a 2 . A low voltage is applied to the first electrode of the color monitor CDT and the video signal is blocked.

또한 상기 오아게이트(OR1)의 고전위 출력신호가 앤드게이트(AND1)의 일측입력단자에 인가되며, 그 앤드게이트(AND1)의 타측입력단자에 수직동기 신호가 인가되어 상기 앤드게이트(AND1)의 출력신호가 플립플롭(FF1)의 클럭단자(CK1)에 인가되고, 그 플립플롭(FF1)의 출력신호는 플립플롭(FF2)의 클럭단자(CK2)에 인가되므로 상기 수직동기신호가 상기 플립플롭(FF1)에 인가된 후 2주기만에 플립플롭(FF2)의 고전위 출력신호는 인버터(I2)를 통해 플립플롭(FF1-FF4)의 리세트 단자(RS1-RS4)에 인가된다.In addition, the Iowa gate (OR 1) the high potential and the output signal is applied to one side input terminal of the AND gate (AND 1), the AND gate (AND 1) the other is applied to the vertical synchronizing signal to an input terminal the AND gate of the ( the output signal of the aND 1) is applied to the clock terminal (CK 1) of the flip-flop (FF 1), the output signal of the flip-flop (FF 1) is applied to the clock terminal (CK 2) of the flip-flop (FF 2) because of the high potential signal is output flip-flop (FF 1 -FF 4) via an inverter (I 2) of the flip-flop (FF 2). 2 jugiman after being applied to the vertical synchronization signal of the flip-flop (FF 1) Li It is applied to the set terminals RS 1 -RS 4 .

따라서 이때 상기 플립플롭(FF1-FF4)은 리세트되며 오아게이트(OR1)의 출력신호는 저전위가 되어 아날로그 스위치부(B1 +)이 인가되는 전원입력단자(a1)에 단락되며, CDT의 제1전극에 높은 전압이 인가되기 때문에 영상신호는 화면에 디스플레이된다. 그 후 앤드게이트(AND1)의 출력신호가 저전위로 되어 플립플롭(FF2)의 출력신호는 저전위가 되며, 절환신호발생부(1)에서 절환신호가 출력되지 않기 때문에 오아게이트(OR1)에서 출력된 저전위 신호가 아날로그 스위치부(2)의 인에이블단자(E)에 인가되므로 칼라 모니터용 CDT의 제1전극에는 높은 전압이 계속 인가된다.Therefore, at this time, the flip-flops (FF 1- FF 4 ) are reset and the output signal of the OR gate (OR 1 ) becomes a low potential and is short-circuited to the power input terminal (a 1 ) to which the analog switch unit (B 1 + ) is applied. Since a high voltage is applied to the first electrode of the CDT, the image signal is displayed on the screen. After that, the output signal of the AND gate AND 1 becomes the low potential, the output signal of the flip-flop FF 2 becomes the low potential, and since the switching signal is not output from the switching signal generator 1, the OR gate OR 1. Since the low potential signal outputted from) is applied to the enable terminal E of the analog switch unit 2, a high voltage is continuously applied to the first electrode of the color monitor CDT.

이상의 상세한 설명에서와 같이 본 고안은 모니터의 모드나 패턴을 절환할 때 화면에 화상이 디스플레이되지 않도록 하여 그 때에 순간 귀선 및 동기불안 현상에 의한 화면의 펄럭임을 방지할 수 있는 효과가 있다.As described in the above description, the present invention has an effect of preventing an image from being displayed on the screen when switching modes or patterns of the monitor, thereby preventing fluttering of the screen due to instantaneous retrace and synchronous anxiety.

Claims (1)

절환신호발생부(1)의 출력신호 및 그의 반전신호가 플립플롭(FF3), (FF4)의 클럭단자(CK3), (CK4)에 각각 인가되도록 하여, 상기 플립플롭(FF3), (FF|4)의 출력단자(Q3), (Q4)를 오아게이트(OR1)의 두 입력단자에 각기 접속하며, 그 오아게이트(OR1)의 출력단자 및 수직동기신호 입력단자(VI)를 앤드게이트(AND1)의 두 입력단자에 접속함과 아울러, 그 앤드게이트(AND1)의 출력단자를 플립플롭(FF1)의 클럭단자(CK1)에 접속하여 이의 출력단자(Q1)를 플립플롭(FF2)의 클럭단자(CK|2)에 접속하고, 상기 플립플롭(FF2)의 출력단자(Q2)를 인버터(I2)를 통해 플립플롭(Q|1-Q4)의 리세트단자(RS1-RS4)와 공통 접속하며, 상기 오아게이트(OR1)의 출력단자를 아날로그 스위치부(2)의 인데이블단자(E)에 접속해 상기 아날로그스위치부(2)의 전원입력단자(a1), (a2)에 제1전원(B1 +) 및 제2전원(B1 +)이 각각 인가되도록 하고, 상기 아날로그스위치부(2)의 출력단자가 CDT의 제1전극에 접속하여 구성한 것을 특징으로 하는 모니터의 모드/패턴절환시 화면 안정회로.To ensure that the output signal and its inversion signal of the switching signal generation unit (1) respectively applied to the flip-flop (FF 3), a clock terminal (CK 3), (CK 4 ) of (FF 4), the flip-flop (FF 3 ), (FF | 4) an output terminal (Q 3), (Q 4 ) to and respectively connected to two input terminals of the Iowa gate (OR 1), the Iowa gate (OR 1) output terminal, and a vertical synchronizing signal input of the terminal (VI) of the aND gate (aND 1) both also connected to the input terminal and, at the same time, the aND gate (aND 1) by connecting the output terminal to the clock terminal (CK 1) of the flip-flop (FF 1) the output thereof in the a flip-flop (Q connected to, and, via an inverter (I 2) to the output terminal (Q 2) of said flip-flop (FF 2) | terminal the (Q 1) clock terminal (2 CK) of the flip-flop (FF 2) 1- Q 4 ), and the output terminal of the OR gate OR 1 is connected to the enable terminal E of the analog switch unit 2 by connecting to the reset terminal RS 1 -RS 4 . power input terminals of the analog switch unit (2) (a 1), (a 2) A first power supply (B 1 +) and the second power supply (B 1 +) are respectively applied to, and the mode of the monitor, characterized in that an output terminal of the analog switch (2) self-configured to connect to a first electrode of CDT / Screen stability circuit during pattern switching.
KR2019880012785U 1988-07-30 1988-07-30 Display stabilizing circuit when change the mode-pattern for monitor KR930004901Y1 (en)

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KR2019880012785U KR930004901Y1 (en) 1988-07-30 1988-07-30 Display stabilizing circuit when change the mode-pattern for monitor

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KR2019880012785U KR930004901Y1 (en) 1988-07-30 1988-07-30 Display stabilizing circuit when change the mode-pattern for monitor

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KR930004901Y1 true KR930004901Y1 (en) 1993-07-26

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