KR920014183A - Synchronous signal processing system with test signal circuit - Google Patents

Synchronous signal processing system with test signal circuit Download PDF

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Publication number
KR920014183A
KR920014183A KR1019900022486A KR900022486A KR920014183A KR 920014183 A KR920014183 A KR 920014183A KR 1019900022486 A KR1019900022486 A KR 1019900022486A KR 900022486 A KR900022486 A KR 900022486A KR 920014183 A KR920014183 A KR 920014183A
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KR
South Korea
Prior art keywords
signal
horizontal
synchronous
circuit
vertical
Prior art date
Application number
KR1019900022486A
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Korean (ko)
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KR930010368B1 (en
Inventor
이문기
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019900022486A priority Critical patent/KR930010368B1/en
Publication of KR920014183A publication Critical patent/KR920014183A/en
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Publication of KR930010368B1 publication Critical patent/KR930010368B1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/04Synchronising
    • H04N5/06Generation of synchronising signals

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Abstract

내용 없음No content

Description

테스트신호회로가 내장된 동기신호처리시스템Synchronous signal processing system with test signal circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 테스트신호회로 시스템의 블럭도, 제3도는 본 발명 테스트신호회로가 내장된 동기신호고 처리시스템의 전체블럭도이다.2 is a block diagram of the test signal circuit system of the present invention, and FIG. 3 is an overall block diagram of a synchronous signal high processing system incorporating the test signal circuit of the present invention.

Claims (2)

복합영상신호가 입력되면 수평ㆍ수직동기신호로 분리하는 동기분리부(2'), 상기 동기분리부에서 입력된 수평동기신호와 톱니파 제너레이터(5')의 톱니파신호와의 주파수를 비교하는 자동주파수제어부(3'), 주파수 차이만큼 에러전압을 발생시켜 주파수를 제어하는 수평오실레이터(6'), 이 주파수를 분주하는 분주회로(7'), 그리고 수평예비구동부(8')를 거쳐 수평동기신호를 출력하는 수평동기신호출력부(H)와, 상기 동기분리부(2')에서 입력된 수직동기신호를 발진시키는 수직오실레이터(4'), 램프신호를 발생시키는 램프제너레이터(9'), 발생된 램프신호에 의해 수직구동부(10')를 구동시켜서 수직동기신호를 출력하는 수직동기신호출력부(V)로 구성된 동기신호처리시스템에 있어서, 입력되는 복합영상신호가 없으면 특정한 패턴을 형성시키는 테스트신호회로부(T)가 첨가된 것을 특징으로하는 테스트신호회로가 내장된 동기신호처리시스템.When the composite video signal is input, the synchronization separator 2 'for separating the horizontal and vertical synchronization signals, and the automatic frequency for comparing the frequency of the horizontal synchronization signal input from the synchronization separator with the sawtooth signal of the sawtooth generator 5'. The horizontal synchronization signal is passed through the control unit 3 ', the horizontal oscillator 6' which generates the error voltage by the frequency difference, and controls the frequency, the frequency divider circuit 7 'which divides the frequency, and the horizontal preliminary driver 8'. A horizontal synchronous signal output unit (H) for outputting a signal, a vertical oscillator (4 ') for oscillating a vertical synchronous signal input from the synchronous separation unit (2'), a lamp generator (9 ') for generating a ramp signal, and generation A synchronous signal processing system comprising a vertical synchronous signal output unit (V) for driving a vertical driving unit (10 ') to output a vertical synchronous signal by means of a ramped ramp signal, wherein a test is performed to form a specific pattern if no composite video signal is inputted signal Robu (T) a circuit test signal is built in the synchronization signal processing system, characterized in that the addition. 제1항에 있어서, 테스트신호회로부(T)는 입력되는 영상신호가 없을 때에만 동기신호변별회로 및 스위치부(11')가 작동되어, 수평오실레이터(6')의 신호를 이용하여 수평ㆍ수직패텬제너레이터(13',15')에서 패턴을 발생시킨 후, 수평ㆍ수직동기제너레이터(12',14')에서 동기신호를 발생시켜 동기시킴으로써 특정패턴을 생성하는 것을 특징으로 하는 테스트신호회로가 내장된 동기신호처리시스템.2. The test signal circuit (T) according to claim 1, wherein the synchronous signal discrimination circuit and the switch section (11 ') are operated only when there is no video signal inputted, so that the test signal circuit section (T) operates horizontally and vertically using a signal of the horizontal oscillator (6'). After the patterns are generated by the pattern generators 13 'and 15', the test signal circuit is characterized by generating a specific pattern by generating and synchronizing the synchronization signals by the horizontal and vertical synchronous generators 12 'and 14'. Synchronized signal processing system. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900022486A 1990-12-29 1990-12-29 Sync-singnal processing apparatus including test-signal circuit KR930010368B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022486A KR930010368B1 (en) 1990-12-29 1990-12-29 Sync-singnal processing apparatus including test-signal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900022486A KR930010368B1 (en) 1990-12-29 1990-12-29 Sync-singnal processing apparatus including test-signal circuit

Publications (2)

Publication Number Publication Date
KR920014183A true KR920014183A (en) 1992-07-30
KR930010368B1 KR930010368B1 (en) 1993-10-16

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Application Number Title Priority Date Filing Date
KR1019900022486A KR930010368B1 (en) 1990-12-29 1990-12-29 Sync-singnal processing apparatus including test-signal circuit

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KR (1) KR930010368B1 (en)

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KR930010368B1 (en) 1993-10-16

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