KR920013104A - Correlation Collision Avoidance Circuit of Data in Microprocessor Using Three Stage Pipeline - Google Patents

Correlation Collision Avoidance Circuit of Data in Microprocessor Using Three Stage Pipeline Download PDF

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Publication number
KR920013104A
KR920013104A KR1019900021822A KR900021822A KR920013104A KR 920013104 A KR920013104 A KR 920013104A KR 1019900021822 A KR1019900021822 A KR 1019900021822A KR 900021822 A KR900021822 A KR 900021822A KR 920013104 A KR920013104 A KR 920013104A
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KR
South Korea
Prior art keywords
microprocessor
input
data
stage pipeline
output
Prior art date
Application number
KR1019900021822A
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Korean (ko)
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KR930007015B1 (en
Inventor
박성배
김상범
함경수
Original Assignee
경상현
재단법인 한국전자통신연구소
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Priority to KR1019900021822A priority Critical patent/KR930007015B1/en
Publication of KR920013104A publication Critical patent/KR920013104A/en
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Publication of KR930007015B1 publication Critical patent/KR930007015B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

내용 없음No content

Description

3단계 파이프 라인을 사용한 마이크로 프로세서에서 데이타의 상관성 충돌방지회로Correlation Collision Avoidance Circuit of Data in Microprocessor Using Three Stage Pipeline

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 회로도.1 is a circuit diagram of the present invention.

Claims (2)

3단게 파이프 라인을 사용한 마이크로 프로세서에서 데이타신호(DST-1), 데이타신호(DST-1)를 1클럭 지연시킨 출력(W), 데이타신호(DST-0), 데이타입력(RA, RB, RC)이 입력단(D0, D1, D2, D3)으로 각각 입력되는 멀티플렉서(1), (2), (3)의 입력단(A), (B)에는 내부제어 입력(RA-A, RA-B), (RB-A, RB-B),(RC-A, RC-B)이 각각(00, 10, 01, 11)으로 입력됨에 따라 입력단(DQ)∼(D3)을 출력단(Z)과 연결하면서 출력(A, W, B, C)을 제어하도록 구성됨을 특징으로한 3단의 파이프 라인을 사용한 마이크로 프로세서에서 데이타의 상관성충돌 방지회로.In the microprocessor using a three-stage pipeline, the output (W), the data signal (DST-0), and the data input (RA, RB, RC) are delayed by one clock. ) Are input to the input terminals D0, D1, D2 and D3, respectively, and the internal control inputs (RA-A, RA-B) are input to the input terminals A and B of the multiplexers 1, 2 and 3, respectively. Input terminals (DQ) to (D3) are connected to the output terminal (Z) as (RB-A, RB-B) and (RC-A, RC-B) are input to (00, 10, 01, 11), respectively. Correlation collision avoidance circuit in a microprocessor using a three-stage pipeline characterized in that it is configured to control the output (A, W, B, C). 제1항에 있어서, 데이타신호(DST-1)는 두래치(4), (5)에 의해 1클럭이 지연된후 출력(W)이 외부로 출력되거나 멀티플렉서(1), (2), (3)의 입력단(D1)으로 궤환되도록하여 데이타의 상관성 재감지시 정상공에 가능하도록한 3단계 파이프 라인을 사용한 마이크로 프로세서에서 데이타의 상관성 방지회로.The data signal DST-1 is outputted after the delay of one clock by the latches 4 and 5, or the output W is output to the outside or the multiplexers 1, 2, 3 Correlation prevention circuit in a microprocessor using a three-stage pipeline that is fed back to the input terminal (D1) of the circuit) to enable normal holes when data is redetected. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900021822A 1990-12-26 1990-12-26 Circuit for checking and preventing data consistency in pipeline processing KR930007015B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900021822A KR930007015B1 (en) 1990-12-26 1990-12-26 Circuit for checking and preventing data consistency in pipeline processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021822A KR930007015B1 (en) 1990-12-26 1990-12-26 Circuit for checking and preventing data consistency in pipeline processing

Publications (2)

Publication Number Publication Date
KR920013104A true KR920013104A (en) 1992-07-28
KR930007015B1 KR930007015B1 (en) 1993-07-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021822A KR930007015B1 (en) 1990-12-26 1990-12-26 Circuit for checking and preventing data consistency in pipeline processing

Country Status (1)

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KR (1) KR930007015B1 (en)

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Publication number Publication date
KR930007015B1 (en) 1993-07-26

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