KR970013700A - Latch implemented with flip-flops and multiplexers - Google Patents
Latch implemented with flip-flops and multiplexers Download PDFInfo
- Publication number
- KR970013700A KR970013700A KR1019950026878A KR19950026878A KR970013700A KR 970013700 A KR970013700 A KR 970013700A KR 1019950026878 A KR1019950026878 A KR 1019950026878A KR 19950026878 A KR19950026878 A KR 19950026878A KR 970013700 A KR970013700 A KR 970013700A
- Authority
- KR
- South Korea
- Prior art keywords
- flip
- flop
- multiplexer
- latch
- multiplexers
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
Landscapes
- Electronic Switches (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
이 발명은 플립플롭과 멀티플렉서로 구현한 래치에 관한 것으로서, 조건을 맞족하면 클럭에 따라 입력을 멀티플렉서의 2단자로 전달하는 플립플롭과, 조건에 따라 입력 신호나 상기 플립플롭에서 공급받는 신호를 출력하는 멀티플렉서로 구성되어, 래치를 대신하여 플립플롭과 멀티플렉서를 사용하여 타이밍 분석을 용이하게 할 수 있는 플립플롭과 멀티플렉서로 구현한 래치에 관한 것이다.The present invention relates to a latch implemented by a flip-flop and a multiplexer. When a condition is met, a flip-flop transfers an input to two terminals of the multiplexer according to a clock, and an input signal or a signal supplied from the flip-flop is output according to a condition. The present invention relates to a latch implemented by a flip-flop and a multiplexer, which is composed of a multiplexer, which can facilitate timing analysis using a flip-flop and a multiplexer instead of a latch.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 이 발명의 실시예에 따른 플립플롭과 멀티플렉서로 구현한 래치의 회로도이다.2 is a circuit diagram of a latch implemented by a flip-flop and a multiplexer according to an embodiment of the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950026878A KR0158657B1 (en) | 1995-08-28 | 1995-08-28 | Latch made by ff and mux |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950026878A KR0158657B1 (en) | 1995-08-28 | 1995-08-28 | Latch made by ff and mux |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970013700A true KR970013700A (en) | 1997-03-29 |
KR0158657B1 KR0158657B1 (en) | 1999-03-20 |
Family
ID=19424691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950026878A KR0158657B1 (en) | 1995-08-28 | 1995-08-28 | Latch made by ff and mux |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0158657B1 (en) |
-
1995
- 1995-08-28 KR KR1019950026878A patent/KR0158657B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0158657B1 (en) | 1999-03-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR920001518A (en) | Semiconductor integrated circuit | |
KR880014475A (en) | Semiconductor integrated circuit device | |
KR900014970A (en) | Synchronous circuit | |
KR950026113A (en) | Data Output Buffer of Semiconductor Memory Device | |
KR920001850A (en) | Flip-flop with scan path | |
KR910002119A (en) | Signal generator | |
KR920002393A (en) | Automotive Input Interface | |
KR900005694A (en) | Pulse generation circuit of predetermined pulse width according to trigger signal | |
KR920015364A (en) | Output buffer circuit | |
KR850008567A (en) | Semiconductor integrated circuit | |
KR970013700A (en) | Latch implemented with flip-flops and multiplexers | |
KR910006986A (en) | Function selection circuit | |
KR900002177A (en) | Compression circuit | |
KR880000961A (en) | Video memory | |
KR970055398A (en) | Latch and Flip-Flop Circuits | |
KR910014785A (en) | Integrated circuit device | |
KR940010792A (en) | Clock multiplexing circuit | |
KR970013736A (en) | Digital signal input circuit | |
KR970024564A (en) | Flip-flop setup time verification circuit | |
KR940003188A (en) | Synchronous Counter Circuit | |
KR910016152A (en) | Synchronization Circuit of Asynchronous Pulse Waveform | |
KR970049289A (en) | Controllable Hardware Reset Circuit | |
KR970055594A (en) | Logic decoding circuit in PPM communication method | |
KR960006272A (en) | Primary / dependent flip-flop | |
KR970049574A (en) | Boundary Scan Output Cell Circuit to Reduce Critical Data Path Delay |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060728 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |