KR940017138A - Stable pulse generator - Google Patents

Stable pulse generator Download PDF

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Publication number
KR940017138A
KR940017138A KR1019920027347A KR920027347A KR940017138A KR 940017138 A KR940017138 A KR 940017138A KR 1019920027347 A KR1019920027347 A KR 1019920027347A KR 920027347 A KR920027347 A KR 920027347A KR 940017138 A KR940017138 A KR 940017138A
Authority
KR
South Korea
Prior art keywords
transistor
pulse generator
delay means
stable pulse
present
Prior art date
Application number
KR1019920027347A
Other languages
Korean (ko)
Other versions
KR950012706B1 (en
Inventor
김재형
윤훈모
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920027347A priority Critical patent/KR950012706B1/en
Publication of KR940017138A publication Critical patent/KR940017138A/en
Application granted granted Critical
Publication of KR950012706B1 publication Critical patent/KR950012706B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits

Landscapes

  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 지연부의 출력을 입력신호로 피드백시켜 일정한 펄스폭을 발생시키도록 하여 이것에 의해 잡음에 의해서 발생된 신호를 차단함으로써 안정된 칩동작을 유지시킬 수 있는 펄스 발생기를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse generator capable of maintaining stable chip operation by feeding back the output of a delay unit to an input signal to generate a constant pulse width thereby cutting off a signal generated by noise.

본 발명은 입력라인에 연결된 제1트랜지스터(N2), 상기 제1트랜지스터(N2)에 연결된 지연수단, 상기 지연수단에 연결된 제2트랜지스터(P2), 상기 제2트랜지스터(P2)와 제1트랜지스터(N2)에 연결된 제3트랜지스터(P1), 및 상기 제3트랜지스터(P1)에 연결된 제4트랜지스터(N1)를 구비하고 있는 것을 특징으로 한다.The present invention provides a first transistor (N2) connected to an input line, a delay means connected to the first transistor (N2), a second transistor (P2) connected to the delay means, the second transistor (P2) and the first transistor ( And a third transistor P1 connected to N2) and a fourth transistor N1 connected to the third transistor P1.

Description

안정 펄스 발생기Stable pulse generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 회로도, 제3도는 작은 펄스가 입력될때 본 발명의 타이밍도, 제4도는 큰 펄스가 입력될때 본 발명의 타이밍도.2 is a circuit diagram of the present invention, FIG. 3 is a timing diagram of the present invention when a small pulse is input, and FIG. 4 is a timing diagram of the present invention when a large pulse is input.

Claims (2)

입력라인에 연결된 제1트랜지스터(N2), 상기 제1트랜지스터(N2)에 연결된 지연수단, 상기 지연수단에 연결된 제2트랜지스터(P2), 상기 제2트랜지스터(P2)와 제1트랜지스터(N2)에 연결된 제3트랜지스터(P1), 및 상기 제3트랜지스터(P1)에 연결된 제4트랜지스터(N1)를 구비하고 있는 것을 특징으로 하는 펄스 발생기.On the first transistor N2 connected to the input line, the delay means connected to the first transistor N2, the second transistor P2 connected to the delay means, the second transistor P2 and the first transistor N2. And a third transistor (P1) connected to the third transistor (P1) and a fourth transistor (N1) connected to the third transistor (P1). 제1항에 있어서, 상기 제2트랜지스터(P2)에 연결된 제5트랜지스터(P3) 및 상기 제5트랜지스터(P3)에 연결된 출력용 인버터를 더 구비하고 있는 것을 특징으로 하는 펄스 발생기.The pulse generator according to claim 1, further comprising a fifth transistor (P3) connected to said second transistor (P2) and an output inverter connected to said fifth transistor (P3). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027347A 1992-12-31 1992-12-31 Stable pulse generater KR950012706B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027347A KR950012706B1 (en) 1992-12-31 1992-12-31 Stable pulse generater

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027347A KR950012706B1 (en) 1992-12-31 1992-12-31 Stable pulse generater

Publications (2)

Publication Number Publication Date
KR940017138A true KR940017138A (en) 1994-07-25
KR950012706B1 KR950012706B1 (en) 1995-10-20

Family

ID=19348511

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027347A KR950012706B1 (en) 1992-12-31 1992-12-31 Stable pulse generater

Country Status (1)

Country Link
KR (1) KR950012706B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140024856A (en) * 2011-02-17 2014-03-03 국립대학법인 홋가이도 다이가쿠 Clock data recovery circuit and wireless module including same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140024856A (en) * 2011-02-17 2014-03-03 국립대학법인 홋가이도 다이가쿠 Clock data recovery circuit and wireless module including same

Also Published As

Publication number Publication date
KR950012706B1 (en) 1995-10-20

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