KR930020440A - Input buffer of memory device - Google Patents

Input buffer of memory device Download PDF

Info

Publication number
KR930020440A
KR930020440A KR1019920003469A KR920003469A KR930020440A KR 930020440 A KR930020440 A KR 930020440A KR 1019920003469 A KR1019920003469 A KR 1019920003469A KR 920003469 A KR920003469 A KR 920003469A KR 930020440 A KR930020440 A KR 930020440A
Authority
KR
South Korea
Prior art keywords
transistor
input
memory device
input buffer
potential
Prior art date
Application number
KR1019920003469A
Other languages
Korean (ko)
Other versions
KR950002025B1 (en
Inventor
김재형
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920003469A priority Critical patent/KR950002025B1/en
Publication of KR930020440A publication Critical patent/KR930020440A/en
Application granted granted Critical
Publication of KR950002025B1 publication Critical patent/KR950002025B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)

Abstract

본 발명은 전력소모를 감속시킬 수 있는 메모리 디바이스의 입력버퍼에 관한 것으로서, 입력버퍼는 버퍼링을 하기 위한 트랜지스터 PAPBNB와, 입력전위를 이용하는 트랜지스터 NA와, 출력을 피드백시켜 주는 인버터 INV1와, 안정된 전위를 유지시켜 주기 위한 캐패시터 C1와, 칩선택신호를 받는 트랜지스터 NC를 구비한다.The present invention relates to an input buffer of a memory device that can reduce power consumption. The input buffer includes a transistor P A P B N B for buffering, a transistor N A using an input potential, and an inverter for feeding back an output. INV 1 , a capacitor C 1 for maintaining a stable potential, and a transistor N C that receives a chip select signal.

본 발명의 입력버퍼는 출력을 피드백시켜 Vcc전원에 연결된 트랜지스터를 오프시킴으로써, 긴 시간주기동안 흐를 수 있는 전류를 차단시켜 전력소모를 감소시킬 수 있다.The input buffer of the present invention can reduce power consumption by cutting off a current that can flow for a long period of time by turning off the transistor connected to the Vcc power supply by feeding back the output.

Description

메모리 디바이스의 입력버퍼Input buffer of memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 입력버퍼회로도.2 is an input buffer circuit diagram of the present invention.

Claims (4)

메모리 디바이스의 입력버퍼로서, 입력전위가 한단자에 인가되는 트랜지스터 NA와, TTL전위의 입력을 버퍼링하여 CMOS전위로 출력시키기 위한 트랜지스터 PAPBNB와, 상기 트랜지스터 PB에 안정된 전위를 유지시켜주기 위한 캐패시터 C1와, 상기 입력버터의 출력을 피드백시켜 Vcc전원에 연결되어 있는 트랜지스터 PA를 온, 오프시켜 주는 인버터 INV1와, 칩선택신호(/CS)를 받는 트랜지스터 Nc를 구비하는 메모리 디바이스의 입력버퍼.As an input buffer of a memory device, a transistor N A to which an input potential is applied to one terminal, a transistor P A P B N B for buffering the TTL potential input and outputting the CMOS potential, and a stable potential to the transistor P B A capacitor C 1 for holding, an inverter INV 1 for turning on and off a transistor P A connected to a Vcc power supply by feeding back the output of the input butter, and a transistor Nc receiving a chip select signal (/ CS). Input buffer of the memory device. 제1항에 있어서, 상기 입력버퍼의 출력이 로우일때, 인버터 INV1를 거쳐 피드백된 신호에 의해 턴온되는 트랜지스터 NA를 통하여 입력전위가 트랜지스터 PB의 소오스에 인가되도록 구성되어 있는 메모리 디바이스의 입력버퍼.The memory device of claim 1, wherein when the output of the input buffer is low, an input potential is applied to a source of the transistor P B through a transistor N A turned on by a signal fed back through an inverter INV 1 . buffer. 제1항에 있어서, 입력이 로우일때, 캐패시터 C1에 충전되어 있던 전하가 방전되어 상기 트랜지스터 PB를 동작시키도록 구성되어 있는 메모리 디바이스의 입력버퍼.The input buffer of the memory device according to claim 1, wherein when the input is low, the electric charge charged in the capacitor C 1 is discharged to operate the transistor P B. 제1항에 있어서, 칩이 선택되지 않을때에는 칩선택신호(/CS)를 받는 트랜지스터 NC를 동작시켜 출력을 로우로 만들며, 이 로우인 신호가 인버터 INV1를 거쳐 피드백되어 트랜지스터 PA를 오프시키도록 구성되어 있는 메모리 디바이스의 입력버퍼.2. The transistor of claim 1, wherein when the chip is not selected, the transistor N C receiving the chip select signal (/ CS) is operated to bring the output low, and this low signal is fed back through the inverter INV 1 to turn off the transistor P A. The input buffer of a memory device, configured to ※ 참고사항: 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the original application.
KR1019920003469A 1992-03-03 1992-03-03 Input buffer of memory device KR950002025B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920003469A KR950002025B1 (en) 1992-03-03 1992-03-03 Input buffer of memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920003469A KR950002025B1 (en) 1992-03-03 1992-03-03 Input buffer of memory device

Publications (2)

Publication Number Publication Date
KR930020440A true KR930020440A (en) 1993-10-19
KR950002025B1 KR950002025B1 (en) 1995-03-08

Family

ID=19329895

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920003469A KR950002025B1 (en) 1992-03-03 1992-03-03 Input buffer of memory device

Country Status (1)

Country Link
KR (1) KR950002025B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100674994B1 (en) 2005-09-10 2007-01-29 삼성전자주식회사 Input buffer for memory device, memory controller and memory system using thereof

Also Published As

Publication number Publication date
KR950002025B1 (en) 1995-03-08

Similar Documents

Publication Publication Date Title
KR880700548A (en) TTL vs. CMOS Input Buffer
KR930003556A (en) Progressive Turn-On CMOS Driver
KR840008075A (en) Semiconductor integrated circuit device for switching control signal generation
KR940027316A (en) Integrated circuit with low power mode and clock amplifier circuit
KR950004534A (en) Level shifter
KR960039569A (en) Booster circuit
KR900002552A (en) Output circuit
KR970008894A (en) Input buffer circuit
KR860004380A (en) Semiconductor memory device
KR880009375A (en) Seamos address buffer
KR930018822A (en) Low power level translator
KR930020440A (en) Input buffer of memory device
KR960019311A (en) Output Potential Reset Circuit of Positive / Negative High Voltage Power Supply
KR980005000A (en) Semiconductor memory device
KR950022103A (en) Voltage on reset circuit
KR890007286A (en) Control signal output circuit
KR960019978A (en) Pulse generator
KR960024820A (en) Signal input buffer with reduced current consumption
KR0119247Y1 (en) Decoder circuit
KR970003935A (en) Logic and level conversion circuit and semiconductor device
KR920001840A (en) Integrator Comparator Circuit
KR100188007B1 (en) Pulse generating circuit
KR970063938A (en) Output buffer circuit of semiconductor device
KR0179801B1 (en) Power supply circuit of dram
KR930022363A (en) Data output buffer using level conversion circuit

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080218

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee