KR960024820A - Signal input buffer with reduced current consumption - Google Patents

Signal input buffer with reduced current consumption Download PDF

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Publication number
KR960024820A
KR960024820A KR1019940040561A KR19940040561A KR960024820A KR 960024820 A KR960024820 A KR 960024820A KR 1019940040561 A KR1019940040561 A KR 1019940040561A KR 19940040561 A KR19940040561 A KR 19940040561A KR 960024820 A KR960024820 A KR 960024820A
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KR
South Korea
Prior art keywords
signal
node
input buffer
input
gate
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KR1019940040561A
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Korean (ko)
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KR100311115B1 (en
Inventor
김정필
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김주용
현대전자산업 주식회사
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Priority to KR1019940040561A priority Critical patent/KR100311115B1/en
Publication of KR960024820A publication Critical patent/KR960024820A/en
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Publication of KR100311115B1 publication Critical patent/KR100311115B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

본 발명은 반도체 소자의 신호 입력버퍼에 관한 것으로 파워 다운 모드시에 일부신호 입력버퍼가 동작함으로써 생기는 전류 소모를 줄이기 위하여, 상기 신호 입력버퍼가 파워 다운 모드시에는 그 동작이 제어되도록 회로를 구현하여 전류 소모를 크게 줄였다.The present invention relates to a signal input buffer of a semiconductor device. In order to reduce current consumption caused by the operation of some signal input buffers in a power down mode, a circuit is implemented such that the operation of the signal input buffer is controlled in a power down mode. The current consumption is greatly reduced.

Description

전류소모를 줄인 신호 입력버퍼.Signal input buffer with reduced current consumption.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 신호 입력버퍼 및 그 주변 회로도.4 is a signal input buffer and a peripheral circuit diagram of the present invention.

Claims (6)

반도체 기억소자가 클럭 신호와 파워 다운 모드와는 파워 다운 모드를 구분하는 신호(CKE)를 가지는 경우에 있어서, 상기 논 파워 다운 모드 시 상기 클럭 신호의 입력 신호에 응답하는 제1입력버퍼와, 상기파워 다운모드시 상기 클럭 신호에 응답하는 제2입력버퍼와, 상기 제2입력버퍼와 접지전압 사이에 형성되고, 소정의 클럭 인에이블 신호의 활성화 입력에 동기하여 활성화되는 소정의 제어신호를 제어 입력하는 스위칭 수단을 구비하는 것을 특징으로 하는 클럭 신호 입력 버퍼.In the case where the semiconductor memory device has a signal (CKE) that distinguishes the power down mode from the clock signal and the power down mode, the first input buffer in response to the input signal of the clock signal in the non-power down mode, and A control input is provided between a second input buffer in response to the clock signal in the power down mode, a predetermined control signal formed between the second input buffer and the ground voltage, and activated in synchronization with an activation input of a predetermined clock enable signal. And a switching means. 제1항에 있어서, 상기 제1입력버퍼는 큰 드라이버의 크기를 갖고, 상기 제2입력버퍼는 작은 드라이버의 크기를 갖는 것을 특징으로 하는 신호 입력버퍼.The signal input buffer of claim 1, wherein the first input buffer has a large driver size, and the second input buffer has a small driver size. 제1항에 있어서, 상기 제2입력버퍼의 제어 신호는 상기CKE신호가 라이징(rising)에서는 상기 CKE 신호의 비동기신호에의해서 발생되고, 상기 CKE신호가 폴링(Falling)에서는 CE신호의 동기 신호의 의해서 발생 되는 것을 특징으로 하는 신호 입력버퍼.The control signal of the second input buffer is generated by the asynchronous signal of the CKE signal when the CKE signal is rising, and the synchronization signal of the CE signal when the CKE signal is falling. Signal input buffer, characterized in that generated by. 제1항에 있어서,상기 제2입력버퍼의 제어 신호는 상기 클럭 신호가 반 클럭된 후 클럭 폴링에 동기된 신호에 의해서 발생되는 것을 특징으로 하는 신호 입력장치.The signal input device of claim 1, wherein the control signal of the second input buffer is generated by a signal synchronized with clock polling after the clock signal is half clocked. 제1항에 있어서, 상기 제2입력버퍼는, 전원전압(Vcc) 및 노드(N22) 사이에 접속되면 게이트가 상기노드(N22)에 연결된 PMOS 트랜지스터(Q5)와, 상기 노드(N22) 및 노드(N24) 에 접속되면 게이트에 기준전압(Vref)이 인가되는 NHOS 트랜지스터(Q7)와, 전원전압(Vcc) 및 노드(N23) 사이에 접속되면 게이터가 상기노드(N22)에 연결된 PMOS 트랜지스터(Q6)와, 상기 노드(N23) 및상기 노드(N24) 사이에 접속되며 게이트에 입력신호(in)가 인가되는 NMOS 트랜지스터(Q8)와, 상기 노드(N24) 및 접지전압(Vss) 사이에 접속되며 게이트에 제어신호(CKEen)가 인가되는 NMOS 트랜지스터(Q30)와, 상기 노드(N23)로부터 출력되는 출력단자(out)로 구성된 것을 특징으로 하는 신호 입력장치.The PMOS transistor of claim 1, wherein the second input buffer includes a PMOS transistor Q5 having a gate connected to the node N22, and a node N22 and a node when a power supply voltage Vcc is connected between the node N22. When connected to N24, the NHOS transistor Q7 to which the reference voltage Vref is applied to the gate, and the PMOS transistor Q6 connected to the node N22 when connected to the power supply voltage Vcc and the node N23. ), An NMOS transistor Q8 connected between the node N23 and the node N24 and to which an input signal in is applied to a gate, and between the node N24 and the ground voltage Vss. And an NMOS transistor (Q30) to which a control signal (CKEen) is applied to a gate, and an output terminal (out) output from the node (N23). 제5항에 있어서, 상기 제어 신호(CKEen) 발생 장치는, 상기 노드(N16) 및 노드(N43) 사이에 접속된 인버터(G22)와, 상기노드(N14) 및 드(N44) 사이에 접속된 인버터(G44)와, 상기 노드(N10,N43,N44)를 입력하여 논리조합된 신호를 노드(N45)에 출력하는 NAND 게이트(G24)와, 상기 노드(N24)로부터 출력되는 CKEen 신호로 구성된 것을 특징으로 하는 신호 입력버퍼.The said control signal CKEen generation apparatus is connected with the inverter G22 connected between the said node N16 and the node N43, and the said node N14 and the node N44. And an inverter G44, a NAND gate G24 for inputting the nodes N10, N43, and N44 to output a logically combined signal to the node N45, and a CKEen signal output from the node N24. Characterized by a signal input buffer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040561A 1994-12-31 1994-12-31 Signal input buffer for memory KR100311115B1 (en)

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KR1019940040561A KR100311115B1 (en) 1994-12-31 1994-12-31 Signal input buffer for memory

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KR1019940040561A KR100311115B1 (en) 1994-12-31 1994-12-31 Signal input buffer for memory

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KR100311115B1 KR100311115B1 (en) 2001-12-15

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100269313B1 (en) * 1997-11-07 2000-12-01 윤종용 Semiconductor memory device for consuming small current at stand-by state
KR100533389B1 (en) * 1998-09-28 2006-02-08 매그나칩 반도체 유한회사 Clock Synchronous Reference Voltage Generator
KR100723774B1 (en) * 2005-12-28 2007-05-30 주식회사 하이닉스반도체 Buffer control circuit for reducing consumption power source and a semiconductor memory device with the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220055741A (en) 2020-10-27 2022-05-04 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100269313B1 (en) * 1997-11-07 2000-12-01 윤종용 Semiconductor memory device for consuming small current at stand-by state
KR100533389B1 (en) * 1998-09-28 2006-02-08 매그나칩 반도체 유한회사 Clock Synchronous Reference Voltage Generator
KR100723774B1 (en) * 2005-12-28 2007-05-30 주식회사 하이닉스반도체 Buffer control circuit for reducing consumption power source and a semiconductor memory device with the same

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