KR920013092A - Variable bitfield make processing circuit - Google Patents

Variable bitfield make processing circuit Download PDF

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Publication number
KR920013092A
KR920013092A KR1019900021836A KR900021836A KR920013092A KR 920013092 A KR920013092 A KR 920013092A KR 1019900021836 A KR1019900021836 A KR 1019900021836A KR 900021836 A KR900021836 A KR 900021836A KR 920013092 A KR920013092 A KR 920013092A
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KR
South Korea
Prior art keywords
bit
processing circuit
variable
make processing
outputting
Prior art date
Application number
KR1019900021836A
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Korean (ko)
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KR930002850B1 (en
Inventor
박성배
김상범
함경수
Original Assignee
경상현
재단법인 한국전자통신연구소
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Priority to KR1019900021836A priority Critical patent/KR930002850B1/en
Publication of KR920013092A publication Critical patent/KR920013092A/en
Application granted granted Critical
Publication of KR930002850B1 publication Critical patent/KR930002850B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

내용 없음No content

Description

가변비트필드 메이크 처리회로Variable bitfield make processing circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 블럭도, 제2도는 본 발명의 디코더의 논리표, 제3도는 본 발명의 배럴쉬프터의 논리표.1 is a block diagram of the present invention, FIG. 2 is a logical table of the decoder of the present invention, and FIG. 3 is a logical table of the barrel shifter of the present invention.

Claims (1)

5비트의 비트폭지정신호를 비트크기만큼 1의 값을 갖는 32비트 신호로 출력하는 디코더(1)와, 상기 디코더(1)의 출력을 입력받아 선택단자(S16)(S8)(S4)(S2)(S1)로 인가되는 오프세트신호의 비트크기만큼 자리이동시켜 출력하는 배럴쉬프터(2)와, 원래 데이타를 상기의 오프세트신호의 비트크기만큼 자리이동시켜 출력하는 배럴쉬프터(3)와, 상기 배럴쉬프터(2)의 출력을 선택단자(S)로 입력받으면서 입력단(A)에 연결된 그라운드(GND)의 0이나 입력단(B)으로 입력되는 원래 데이타를 비트마다 선택하여 출력하는 그 입력 1출력 멀티플렉서(4)들로 구성됨을 특징으로 하는 가변비트 필드 메이크 처리회로.A decoder 1 for outputting a 5-bit bit width designation signal as a 32-bit signal having a value of 1 by bit size, and a selection terminal S16, S8, S4 that receives the output of the decoder 1; A barrel shifter 2 for shifting and outputting the bit shifted by the bit size of the offset signal applied to S2 and S1, and a barrel shifter 3 for shifting the original data by the bit size of the offset signal and outputting it; The input 1 which selects and outputs the original data inputted to the input terminal B or 0 of ground GND connected to the input terminal A while receiving the output of the barrel shifter 2 through the selection terminal S. A variable bit field make processing circuit comprising: output multiplexers (4). ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900021836A 1990-12-26 1990-12-26 Variable bit field making processor circuit KR930002850B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900021836A KR930002850B1 (en) 1990-12-26 1990-12-26 Variable bit field making processor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021836A KR930002850B1 (en) 1990-12-26 1990-12-26 Variable bit field making processor circuit

Publications (2)

Publication Number Publication Date
KR920013092A true KR920013092A (en) 1992-07-28
KR930002850B1 KR930002850B1 (en) 1993-04-12

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ID=19308510

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021836A KR930002850B1 (en) 1990-12-26 1990-12-26 Variable bit field making processor circuit

Country Status (1)

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KR (1) KR930002850B1 (en)

Also Published As

Publication number Publication date
KR930002850B1 (en) 1993-04-12

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