KR920010460A - Memory subsystem with two bus structures - Google Patents

Memory subsystem with two bus structures Download PDF

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Publication number
KR920010460A
KR920010460A KR1019900019439A KR900019439A KR920010460A KR 920010460 A KR920010460 A KR 920010460A KR 1019900019439 A KR1019900019439 A KR 1019900019439A KR 900019439 A KR900019439 A KR 900019439A KR 920010460 A KR920010460 A KR 920010460A
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KR
South Korea
Prior art keywords
bus
control
interface
interfaces
memory subsystem
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Application number
KR1019900019439A
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Korean (ko)
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KR920009444B1 (en
Inventor
현상용
Original Assignee
정몽헌
현대전자산업 주식회사
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Priority to KR1019900019439A priority Critical patent/KR920009444B1/en
Publication of KR920010460A publication Critical patent/KR920010460A/en
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Publication of KR920009444B1 publication Critical patent/KR920009444B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

내용 없음.No content.

Description

2개의 버스 구조를 갖는 메모리 서브 시스템Memory subsystem with two bus structures

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

도면은 본 발명에 따른 2개의 버스 구조를 갖는 메모리 서브시스템의 블럭도.Is a block diagram of a memory subsystem having two bus structures in accordance with the present invention.

Claims (1)

메모리 서브시스템에 있어서, 제1어드레스 인터 페이스(1), 제1데이타 인터 페이스(3), 제1콘트롤 인터 페이스(5) 및 버스 리퀘스터(7)각각은 제1버스(12)에 각기 병렬접속되고, 제2버스(13)에는 제2어드레스 인터 페이스(2), 제2데이타 인터 페이스(4) 및 제2콘트롤 인터 페이스(6)가 각기 병렬 접속되고, 상기 제1및 제2어드레스 인터 페이스(1 및 2)는 어드레스 디코더(10)를 경유해 다이나믹 메모리 론트롤부(9)에 접속되는 동시에 상기 버스 리퀘스터(7)에 접속되고, 상기 제1및 제2데이타 인터 페이스(3및 4)는 서로 접속된 체로 상기 버스 리퀘스터(7)에 접속되는 동시에 메모리 어레이(11)에 접속되고, 상기 제1및 제2콘트롤 인터 페이스(5및 6)각각은 버스 콘트롤 스윗칭부(8)를 경유해, 상기 다이나믹 메모리 콘트롤부(9)에 접속되고, 상기 버스 리퀘스터(7)는 상기 버스 콘트롤 스위칭부(8), 상기 제1및 제2콘트롤 인터 페이스(5및 6)에 접속구성되며, 상기 제1 및 제2콘트롤 인터 페이스(5및 6)각각은 상기 제1및 제2데이타 인터 페이스(3및 4)각각에 접속 구성되는 것을 특징으로 하는 2개의 버스 구조를 갖는 메모리 서브시스템.In the memory subsystem, the first address interface 1, the first data interface 3, the first control interface 5 and the bus requester 7 are each parallel to the first bus 12. A second address interface 2, a second data interface 4 and a second control interface 6 are connected in parallel to the second bus 13, respectively, and the first and second address interlaces are connected to each other. Phases 1 and 2 are connected to the dynamic memory loan control unit 9 via an address decoder 10 and to the bus requester 7, and to the first and second data interfaces 3 and 2, respectively. 4) is connected to the bus requester 7 in a state of being connected to each other, and to the memory array 11, and the first and second control interfaces 5 and 6 are respectively connected to the bus control switching unit 8; Is connected to the dynamic memory controller 9, and the bus requester 7 is connected to the bus. A control switching unit 8 is connected to the first and second control interfaces 5 and 6, and the first and second control interfaces 5 and 6 are each of the first and second data interfaces. 2. A memory subsystem with two bus structures characterized in that they are connected to faces 3 and 4, respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900019439A 1990-11-29 1990-11-29 Memory system with two bus structure KR920009444B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900019439A KR920009444B1 (en) 1990-11-29 1990-11-29 Memory system with two bus structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900019439A KR920009444B1 (en) 1990-11-29 1990-11-29 Memory system with two bus structure

Publications (2)

Publication Number Publication Date
KR920010460A true KR920010460A (en) 1992-06-26
KR920009444B1 KR920009444B1 (en) 1992-10-16

Family

ID=19306719

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900019439A KR920009444B1 (en) 1990-11-29 1990-11-29 Memory system with two bus structure

Country Status (1)

Country Link
KR (1) KR920009444B1 (en)

Also Published As

Publication number Publication date
KR920009444B1 (en) 1992-10-16

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