KR910016078A - Hat Stack Cell Manufacturing Method and Structure - Google Patents

Hat Stack Cell Manufacturing Method and Structure Download PDF

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Publication number
KR910016078A
KR910016078A KR1019900002346A KR900002346A KR910016078A KR 910016078 A KR910016078 A KR 910016078A KR 1019900002346 A KR1019900002346 A KR 1019900002346A KR 900002346 A KR900002346 A KR 900002346A KR 910016078 A KR910016078 A KR 910016078A
Authority
KR
South Korea
Prior art keywords
oxide film
forming
polysilicon
buried contact
hat
Prior art date
Application number
KR1019900002346A
Other languages
Korean (ko)
Inventor
김정규
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900002346A priority Critical patent/KR910016078A/en
Publication of KR910016078A publication Critical patent/KR910016078A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

모자형 스택셀 제조 방법 및 구조Hat Stack Cell Manufacturing Method and Structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (A) ~ (E)는 본 발명에 따른 모자형상 스택셀 제조방법의 설명을 위한 구조 단면도, 제3도는 본 발명에 따른 모자형상 스택셀 구조의 평면도.2 (A) to (E) is a cross-sectional view for explaining the hat-shaped stack cell manufacturing method according to the present invention, Figure 3 is a plan view of the hat-shaped stack cell structure according to the present invention.

Claims (3)

P - si기판(1)에 필드산화막(2)과 게이트패턴(3) 및 n + 영역 (4)을 형성한후 산화막(5)과 질화막(6) 및 산화막(7)을 차례로 형성하는 공정과, 상기 산화막(7) 형성후 배리드콘택(8)을 파고 배리드콘택(8) 양측에 폴리 실리콘 기둥(9)을 만드는 공정과, 상기 폴리실리콘기둥(9) 형성후 질화막(6)을 에치스톱으로하여 산화막(7)을 제거하는 공정과, 상기 공정후 노드전극(10)과 캐패시턴스산화막(11) 및 플레이트전극(12)을 형성하는 공정과, 상기 플레이트전극(12) 형성후 산화막(13)과 비트선콘택(14)을 형성하는것을 특징으로하는 모자형 스택셀 제조방법.Forming a field oxide film 2, a gate pattern 3, and an n + region 4 on the P-si substrate 1, and then sequentially forming an oxide film 5, a nitride film 6, and an oxide film 7; Digging the buried contact 8 after the oxide film 7 is formed and forming the polysilicon pillar 9 on both sides of the buried contact 8, and etching the nitride film 6 after forming the polysilicon pillar 9. Removing the oxide film 7 at a stop, forming the node electrode 10, the capacitance oxide film 11, and the plate electrode 12 after the step; and forming the oxide film 13 after the plate electrode 12 is formed. And a bit line contact (14). 제 1 항에 있어서, 배리드콘택(8)을 파고 폴리실리콘을 얹은다음 RIE을 하여 폴리실리콘기둥(9)을 형성하는 것을 특징으로하는 모자형 스택셀 제조방법.The method according to claim 1, wherein the buried contact (8) is dug, the polysilicon is loaded and the RIE is formed to form a polysilicon column (9). 배리드콘택(8)의 양측에 질화막(6)보다 높이 형성되어 캐패시턴스산화막 (11)이 모자형을 이루도록하여 캐패시턴스가 증가되도록하는 폴리실리콘기둥(9)을 포함하여 구성된 것을 특징으로 하는 모자형 스택셀구조.Cap-shaped stack characterized in that it comprises a polysilicon pillar (9) formed on both sides of the buried contact (8) higher than the nitride film (6) so that the capacitance oxide film (11) to form a cap shape to increase the capacitance Cell structure. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900002346A 1990-02-23 1990-02-23 Hat Stack Cell Manufacturing Method and Structure KR910016078A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900002346A KR910016078A (en) 1990-02-23 1990-02-23 Hat Stack Cell Manufacturing Method and Structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900002346A KR910016078A (en) 1990-02-23 1990-02-23 Hat Stack Cell Manufacturing Method and Structure

Publications (1)

Publication Number Publication Date
KR910016078A true KR910016078A (en) 1991-09-30

Family

ID=67468513

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900002346A KR910016078A (en) 1990-02-23 1990-02-23 Hat Stack Cell Manufacturing Method and Structure

Country Status (1)

Country Link
KR (1) KR910016078A (en)

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