KR910007392B1 - Scroll window signal generation circuit - Google Patents

Abstract

The circuit for generating the scroll window signal to display the dual pictures horizontally or vertically on a monitor by comparing the scroll mode output signals according to the +,key inputs includes a 1st input stage (10) for receiving and sending the input signal of the reference clock to an OR gate (OR) a 2nd input stage (20), a 1st-2nd counters (CNT1,CNT2) for counting the horizontal region covering one period of the horizontal sync. with the clock supplied from output of the OR gate, an inverter (N1-N3) for inverting output of a 3rd counter (CNT3), and NAND gates (NA1-NA2) for generating and sending the window reception signals to the inputs of AND gates (AND1,AND2).

Description

Scroll Window Signal Generation Circuit of Digital Image Processing Equipment

1 is a circuit diagram according to the present invention.

2 is a working principle according to the present invention.

3 is an operational waveform diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

CNT1-CNT3: 1-3 Counter OR: Oagate

NOR: Noah gate AND1-AND2: And gate

NA1-NA2: NANDGATE

XOR2-XOR5: Exclusive Oagate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scroll window signal generating circuit of a digital imaging apparatus, and more particularly, to a scroll window signal generating circuit which distinguishes two screen sources from left and right and displays them simultaneously. Techniques that allow two or more screen sources to be displayed on one screen at the same time include a picture display method using picture-in-picture and a scroll display method. The picture-in-picture method reduces and inserts a small screen having a different screen source on the main screen, and has the advantage of displaying all the original source screens, but is displayed in a small screen so that it can be properly viewed at a predetermined distance. There is no drawback. In the scroll display method, two screens having different screen sources are displayed at the same time by being divided into upper, lower, left and right on the screen, and the two screens are divided into the same size according to the window selection. Otherwise, if one screen source is enlarged, another screen source is displayed as small as it is hidden. In the scroll window method, a part of the full screen can be seen as it is in a size that fits the screen frame, but the part that is scrolled and hidden cannot be displayed.

In the conventional scrolling method, when a plurality of screens are selected and displayed on a screen, a window for displaying a desired portion is displayed by setting a window for displaying left, right, up, and down selection keys according to the purpose. However, the upper, lower, left, and right scroll windows have different screen setting window pulses according to the scroll type of the screen. In addition, since each scroll type is selected and used from the decoded window signal, a selection circuit for performing this is complicated, and the logic signal processing capacity is increased.

Accordingly, an object of the present invention is to provide a scroll mode output signal for distinguishing a predetermined mode by an input signal of an up / down (+) (-) key indicating a scroll form of the main horizontal synchronous counter output signal conventionally used in a digital controller. In comparison, a counter output suitable for the scroll mode is obtained from the comparison result to obtain a final scroll window signal, and a circuit is provided for dividing the screen on the display device corresponding to the predetermined mode vertically to obtain a desired scroll display function. .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, in which the first means 100 inputs a basic clock signal (3.58MHZ) input to the first input terminal 10 to the oragate OR, and to the second input terminal 20. The actual data read synchronization signal generated in the input synchronous circuit separation (not shown) is input to the clear terminal CLR of the first and second counters CNT1 and CNT2, and is input to the input of the second input terminal 20. Accordingly, the output of the OR gate is input to the clock terminals CK of the first and second counters CNT1 and CNT2 to count the horizontal lines at the first and second counters CNT1 and CNT2. The second means 200 inputs the scroll selection signal of the fifth input terminal 50 to the load terminal of the third counter CNT3, and scrolls the user through the third and fourth input terminals 30 and 40. The left and right selection signals are input to the AND gates AND1 -AND2, and the outputs of the AND gates AN1-AN2 are input to the count up and down counts of the third counter CNT3. The third counter CNT3 operates in the rising and falling counting mode, and the initial positions at which the input terminals A, B, C, and D of the third counter CNT3 become intermediate positions of the scroll window are set. Since A, B, C, and D = 0, ^{1, 1,} 0, converting to decimal results in 6 = 0 ² +2 ² +2 ¹ +0. The third means 300 compares the counting values output from the first and second means 100 and 200 to the exclusive OA gates XOR2-XOR5, and logicalizes them at the NOA gate NOR. SW) generates a scroll window signal and inputs the OR gate to OR to maintain a constant window by setting a desired window at a corresponding position. The fourth means 400 inverts the output of the second means 200 from the inverter N1N4 and inputs the NAND gates NA1 and NA2 to the left and right sides of the screen at the NAND gates NA1 and NA2. It is configured to generate a window recognition signal corresponding to the end of the right side and input the same to the AND gates AND1 and AND2.

FIG. 2 is a diagram illustrating an embodiment of the present invention, in which a scroll window generated at a noar gate NOR of FIG. 1 when the scroll screen 188 divided vertically is divided into 12 scroll positioning modes. The main screen on the left side and the digital sub screen on the right side are displayed according to the output signal generated from the selection signal output terminal SW. That is, the size of the left and right screens is proportionally changed according to how the scroll window selection signal SW is changed. The window selection shown in FIG. 2 is a position where the scroll function is automatically set in the initial on state, and the initial stage AD of the third counter CNT3 is first set to 0110 (6), so that the scroll initial position 288 is set. )

For example, the initial value of the third counter CNT3 is 0, 1, 1, 0 for the input terminals A, B, C, and D, so that the output terminals QA, QB, QC, and QD are 0, 1, 1, 0. The output of the NAND gates NA1-NA2 becomes "high" when it is input to the exclusive OA gates XOR2-XOR5 and is input to the NAND gates NA1 and NA2 through the inverters N1-N4. .

The “high” is input to the NAND gates AND1 and AND2 so that the scroll up / down signals input to the third and fourth input terminals 30 and 40 are normally input.

On the other hand, the initial value 0110 of the output terminals (QA-QD) of the third counter (CNT3) is input to the exclusive oragate (XOR2-XOR5), respectively, the oragate at the first and second counters (CNT1, CNT2) When the output of (OR) is counted and the output terminal QA-QD of the second counter CNT2 and the output reach " 0110 ", the output of the exclusive ogate XOR2-XOR5 becomes " low ". The output terminals QA-QD of the second counter CNT2 become “0, 1, 1, 0”, so that the output terminals QA-QD of the first and second counters CNT1 and CNT2 are all 8 bits. When the output terminals QA-QD of the counter CNT2 are the upper four bits, 0, 1, 1, 0 = 0 + 32 + 64 + 0 = 96 (0 ⁴ +2 ⁵ +2 ⁶ +0 ⁷ ), and thus the second When the counting value between the window areas of the figure has a value of about 16, it can be seen that since the derotation position is 6 when the function is on scroll, 16 × 6 = 96.

Therefore, when the output of the noar gate NOR becomes “high” and is input to the oragate OR, the clock input to the first input terminal 1 by the “high” logic is cut off at the oragate OR. Since the first and second counters CNT1 and CNT2 do not receive any more clocks, the counting operation is stopped to keep the window region "6".

However, when the up key is input to the third input terminal 30, the output terminals QA-QD of the third counter CNT3 become “1, 1, 1, 0” to be input to the exclusive OA gates XOR2-XOR5. Since the output of the exclusive exclusive oar gate XOR2 becomes high, the output of the noor gate NOR becomes low, and the clock is received by the oragate OR again and the first and second counters CNT1 and CNT2 are applied. The output terminal QA of the second counter CNT2 becomes " high ", which is inputted to the clock terminal CK of the second counter CNT2, so as to output the output terminals QA-QD of the third counter CNT3. When 1, 0 is reached, the output of the NOR gate becomes “high” as described above, and the operation of the second counters CNT1 and CNT2 is stopped to maintain the position of the window region 7 again. .

However, when the falling signal is input to the fourth input terminal 40, the scroll position can be set in reverse according to the window region. The NAND gates NA1 and NA2 set limits on the left and right sides of the window region. When the output of the NAND gate NA1 is “low,” the NAND gates NA1 and NA2 cannot receive the rising mode signal of the third input terminal 30, so that the NAND gates NA1 and NA2 are the rightmost. Is set. This is a value at which the output terminals QA-QD of the third counter CNT3 are "1, 0, 1, 1" (= 11), and the output of the NAND gate NA1 is "low". That is, it is the position which becomes the window area "11" of FIG. 2, and when the output of NAND gate NA2 is "low", since the rising mode signal of the 4th input terminal 40 cannot be received, the leftmost side is set. This is a value at which the output terminals QA-QD of the third counter CNT3 become "0, 0, 0, 1" (= 1), and the output of the NAND gate NA2 is "low". That is, it becomes the position used as the window area "1" of FIG. Accordingly, it can be seen that the leftmost side is set when the third counter CNT3 continues the rising and falling counting and reaches the above value.

3 is an operation timing diagram of FIG. 1 according to the present invention, in which 3a is a read start signal input to the first input and second input terminal 20, and 3d and 3f are first views. An output signal of the output terminals QA-QD of the second counter CNT2, 3g is a scroll mode stage control input signal input to the fifth input terminal 50, and 3h is a signal of the third input terminal 30. (3i) is an output data waveform of the third counter (CNT3), (3j) is a scroll window signal waveform output from the NOR gate (NOR), and (3k)-(3n) are the third waveforms. The change waveform is output from the third counter CNT3 according to the inputs of the four input terminals 30 and 40.

Hereinafter, a specific embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3 above. When the user turns on the scroll function key in FIG. 1, the scroll pulse is first introduced into the high pulse (+). The scroll selection signal of the fifth input terminal 50 is accepted as an active " low " state and thus is input as (3g, 3k). Subsequently, a read start signal is generated by a main sync signal generation circuit (not shown) upon scrolling to clear the first and second counters CNT1 to CNT2. At this time, the first and second counters CNT1 to CNT2 start counting from address zero. When the full screen 188 is set to 12 modes as shown in FIG. 2, one window area is counted 16 times, and one window area is generated and cleared in the next synchronization period. According to (16 x 11 = 176), the window selection signal is generated. That is, the scroll window requires 11 windows in accordance with each screen scroll position, and the automatic scroll position 288 is the initial position as shown in FIG.

The principle example of FIG. 2 will be described in detail with reference to FIG. 1 with reference to FIG. 1. The first and second counters CNT1 are controlled by the third input terminal 30 which is a read start signal input to the second input terminal 20. CNT2) is cleared, and the read start signal is for matching the start of the actual video signal except for the synchronization signal of the video composite signal.

) 그 결과 8비트중 상기 5비트 카운트 출력은 제3도(3b)-(3f)와 같이 출력됨을 알수 있다. 이때 사용자가 스크롤키를 입력하면 제5입력단(50)으로 제3도(3g),(3k)와 같은 스크롤신호가 발생되어 제3카운터(CNT3)의 로드단(LOAD)을 액티브한다. 상기 제3카운터(CNT3)의 액티브와 동시에 제3카운터(CNT3)의 입력단(A,B,C,D)의 상태가 "0110"이므로 제3카운터(CNT3)의 출력단(QA-QD)의 출력은 (3i)와 같이 출력된다. 이때 익스클루시브 오아게이트(XOR2-XOR5)에서 제2카운터(CNT2)에서 카운팅되는 값과 비교한다. 제2카운터(CNT2)의 출력단(QA-QD)이 "0, 1, 1, 0"일 때 익스클루시브 오아게이트(XOR2-XOR5)의 출력은 "로우" 가되고 이를 노아게이트(NOR)를 통과하면 제2도의 스크롤 화면의 윈도우의 중간위치("6")에 해당하는 윈도우 선택신호가 출력함과 동시에 상기 선택신호를 오아게이트(OR)에 입력시켜 제1,2카운터(CNT1-CNAT2)의 펄스입력을 중지하므로 제1,2카운터(CNT1,CNT2)의 카운팅이 중지된다. 이때 2화면소스에 대해 같은 사이즈로 나누어 보게 되는 예이다. 즉 두사람의 얼굴을 표시할 수 있도록 하는 화면소스라면 상기 각 두사람의 얼굴의 반만 표시되는 상태가 된다.The reference frequency clock (3.58MHZ) signal input to the first input terminal 10 after the first and second counters CNT and CNT2 are cleared by the signal (3a) of FIG. When the input clock signal is input to the clock terminals CK of the first and second counters CNT1 and CNT2 and the input clock signal is counted, the signal output to the output terminal QD of the first counter CNT1 is output as shown in 3b. When the ripple carry signal of the first counter CNT1 is received by the second counter CNT2 and the input clock signal of the OR gate OR is counted, the output of the output terminals QA-QD of the second counter CNT2 is ( It is outputted as 3c)-(3f) and input to the exclusive oragate (XOR2-XOR5). One horizontal picture can be performed by the first and second counters CNT1 and CNT2 during one horizontal synchronization signal period of the video signal. If you count only about 192, you can count all valid screen sections.

As a result, it can be seen that the 5-bit count output of the 8 bits is output as shown in FIGS. 3b and 3f. At this time, when the user inputs the scroll key, a scroll signal as shown in FIGS. 3G and 3K is generated to the fifth input terminal 50 to activate the load terminal LOAD of the third counter CNT3. Since the state of the input terminals A, B, C, and D of the third counter CNT3 at the same time as the third counter CNT3 is active, the output of the output terminals QA-QD of the third counter CNT3 is "0110". Is output as (3i). At this time, the value is counted at the second counter CNT2 at the exclusive oragate XOR2-XOR5. When the output terminals QA-QD of the second counter CNT2 are "0, 1, 1, 0", the output of the exclusive oar gates XOR2-XOR5 becomes "low" and the noar gate NOR is turned on. When passing, the window selection signal corresponding to the middle position ("6") of the window of the scroll screen of FIG. 2 is output, and the selection signal is input to the OR gate OR so that the first and second counters (CNT1-CNAT2) Since the pulse input is stopped, counting of the first and second counters CNT1 and CNT2 is stopped. In this case, the two screen sources are divided into the same size. In other words, if it is a screen source for displaying two faces, only half of each of the two faces is displayed.

If the user manipulates the (+) key when the window is selected to view the left screen of the left and right screens, the third input terminal 30 is input to the AND gate AND1 as shown in (3h). The output of the NAND gate NA1 input to the type force terminal of the AND gate AND1 is “high” as long as it does not become the rightmost side, so that the input of the third input terminal 30 is received from the AND gate AND1 and the third counter ( CNT3) is input to the rising count end up. In this case, the third counter CNT3 may be in the rising counting mode as shown in “0110” through 3i, and may be increased to “0110 → 0111” to the output terminal QA-QD and output until the final “1101”. The output of the third counter CNT3 is compared with the output of the output terminals QA-QD of the second counter CNT2 at the exclusive OA gates XOR2-XOR5, and the second and third counters CNT2- When the outputs of the CNT3) are all the same, the outputs of the exclusive oar gates XOR2-XOR5 are all "low", and the scroll window signal is generated "high" by the noar gate NOR as shown by (3j). As a result, the clock input is blocked by the OR gate OR1 to stop the operation of the second counters CNT1 and CNR2, thereby maintaining this state. That is, eight regions of the selected window point 2 are selected, and when the scroll window is generated, the first and second counters CNT1 and CNT2 are clocked by the scroll window signal inputted to the OR gate OR. "High" is always entered and counting stops. If the (-) key is input, it is input to the AND gate AND2 as (3m) through the fourth input terminal 40. The output of the NAND gate NA2 as the type force terminal of the AND gate AND2 is “high” as long as it is not the leftmost side of the window, and thus can receive the falling mode signal of the fourth input terminal 40. At this time, the third counter CNT3 is set in the falling count mode by the output of the AND gate AN2, and the output of the output terminals QA-QD of the third counter CNT3 is down counted so that the exclusive OOR gate XOR1-. XOR5) is compared with the output of the second counter CNT2. At this time, when the output of any one of the exclusive OA gates XOR2-XOR5 becomes “high”, the output of the NOA gate NOR becomes “low” so that the first input terminal 10 is again in the OR gate OR. Receive the clock and start counting again at the first and second counters CNT1 and CNT2. If the output of the second counter CNT1 is the same as the output of the third counter CNT3, the exclusive oar gates XOR2-XOR5 The output of the " low " and the output of the noar gate NOR become " high " to block the clock input of the oragate OR to maintain this state.

Therefore, when both of the exclusive oragates XOR2-XOR5 become "low" according to the comparison value, the output of the NOA gate NOR becomes "high" and the split position 288 is shifted to the left. At this time, the window is set such that the left screen of the second scroll screen 188 is reduced, and the right sub digital screen is displayed large.

As shown in (3k)-(3n) of FIG. 3m (3m), the window of the scroll screen 188 of FIG. 2 is freely selected in accordance with the input change of the third and fourth input terminals 30,40. According to the (+) (-) key operation, the inputs of the third and fourth input terminals 30 and 40 are changed, and the output of the third counter CNT3 output terminal QA-QD is 0001 corresponding to the leftmost window. In the case of 1011 corresponding to the rightmost window, the outputs of the NAND gates NA1 and NA2 become "low" and are input to the AND gates AND1 and AND2 so that the outputs of the AND gates AND1 and AND2 become "low". Since no key input of the third counter CNT3 is accepted, the designated scroll screen window of FIG. 2 is not out of range.

In the embodiment of the present invention, the number of scroll windows is set to 11, but in order to increase the number of scroll windows, the scroll function can be easily upgraded by enlarging and applying 5bit-6bit → 7bit → 8bit instead of 4bit.

As described above, the horizontal window counter used for the picture-in-picture or other digital functions can be used together, and the up / down counter can be used to generate the scroll window signal easily and efficiently.

Claims (1)

In the scroll window signal generation circuit of the digital image processing apparatus, the basic clock signal input to the first input terminal 10 is connected to the oragate OR and is generated in the synchronous separation input to the second input terminal 20. First to input a real data read synchronization signal as a clear signal to input the output of the OR gate as a clock according to the input of the second input terminal 20 to count the horizontal region of the horizontal synchronization period. It is connected to input the scroll selection signals of the counters CNT1 and CNT2 and the fifth input terminal 50 to the load signal stage, and inputs the user's scroll window left and right selection signals through the third and fourth input terminals 30 and 40. A third counter CNT3 for inputting the selection signal and the left and right recognition signals of the scroll window to the AND gates AN1 and AN2 to set up and down modes to generate a scroll window setting signal by counting; - A scroll window signal is generated from the comparison result of the exclusive oragate XOR2-XOR5 comparing the output counting values of the three counters CNT1-CNT3 and the exclusive oragate XOR2-XOR5, and the oragate Noah gate (NOR) to be input to the (OR) to block the clock input to be set according to the selected window, and the output of the third counter (CNT3) by the inverter (N1-N3) to invert the predetermined left, And a NAND gate (NA1-NA2) for generating a window recognition signal corresponding to the end of the right side and inputting the input signal to the AND gates (AND1-AND2).

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