JPS5857751B2 - cathode ray tube display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cathode ray tube display device, and more particularly to an improvement in a horizontal line display circuit that displays horizontal lines that serve as a guide for vertical position.

As is well known, there is an interlaced scanning cathode ray tube display device that divides the field display screen into pixel units and displays pixel memory data corresponding to each pixel as a luminance signal. A horizontal line display circuit is also added to display horizontal lines as a guide.

However, conventional horizontal line display circuits use the n-th and (n+1)-th horizontal scanning signals obtained by decoding the output of the horizontal scanning counter as luminance signals, regardless of the first field and second field scanning timings. Therefore, as shown in Figure 1, the width of the displayed horizontal line L is as much as four horizontal scanning lines, and it is not suitable as a line indicating the boundary between pixel D1 and pixel D2. It is appropriate.

That is, when the n-th and (n+1)-th horizontal scanning signals are used as luminance signals regardless of field scanning,
In the first field F1, the horizontal scanning lines shown as Yn(Fl) and Yn+1 [F1] in FIG.
] The horizontal scanning line indicated by the symbol " ] lights up, and the width of the horizontal line L becomes four horizontal scanning lines.

For this reason, the line is superimposed on the luminance signal based on the pixel memory data, making the display difficult to see, and is not suitable as a line indicating the boundary between pixels.

The present invention has been made to solve these drawbacks, and its purpose is to display a horizontal line using only the two horizontal scanning lines closest to the boundary between vertically arranged pixels. An object of the present invention is to provide a cathode ray tube display device.

Hereinafter, the present invention will be described in detail using illustrated embodiments.

FIG. 2 is a circuit diagram showing an embodiment of a horizontal line display circuit which is a main part of the present invention.

In the same figure, 1 is a vertical drive signal VD and a horizontal drive signal H.
D, the field discrimination circuit discriminates the first field scanning period F1 and outputs an "H" level signal FLD1 representing the first field scanning period F1, as shown in the time chart of FIG. The multi-shot multi 10 outputs a one-shot pulse WP with a pulse width t expressed as -<t<h (h; 1 horizontal scanning time), which is triggered by the timing of the first horizontal scan, and the horizontal synchronization signal is output during the generation of the one-shot pulse WP. If HD is present, the Nant gate 11 outputs the signal FID at the 'L' level, and the 'L' level signal FID is output.
“Reset by the vertical drive signal VD of level “
The flip-flop 12 is set by a signal FID at an L" level and outputs a signal FLDI at an "H" level indicating the first field scanning period from the cent output Q.

2 is a horizontal scanning counter that counts the horizontal drive signal HD using the vertical drive signal VD as a reference, and outputs the count output as a horizontal scanning period position signal LC; 3 is a horizontal scanning counter that decodes the horizontal scanning period position signal LC; and the first (
A decoding circuit that outputs pulse signals Pn t Pn-1-t each corresponding to one horizontal scanning time indicating the (n+1)th horizontal scanning period, wherein the horizontal scanning period position signal LC is at the nth horizontal scanning period position. The Nantes gate 30 outputs the pulse signal Pn at the "L" level when corresponding, and the output P,n ("L" level) of the Nantes gate 30 is taken in at the rising timing of the horizontal synchronizing signal HD, and the "L"
A pulse signal Pn+ indicating the (n+1)th horizontal scanning period by delaying the level capture input by one horizontal scanning period.
1, and a flip-flop 31 that outputs the signal as 1.

4 outputs the pulse signal Pn+1 indicating the (n+1)th horizontal scanning period as the "H" level luminance signal B in the first field scanning period F1 according to the output signal FLD1 of the field discrimination circuit 1, and in the second field scanning period At F2, the pulse signal Pn indicating the n-th horizontal scanning period is set to “H”.
This is a gate circuit that outputs a brightness signal B of "level", and includes an inverter 40 that inverts the signal FLD1, an output signal FLD1 of the inverter 40 is "L" level, and a signal Pn-1-1 is "L" level. When the signal FLD1 is at the "L" level and the signal Pn is at the "L" level, the OR gate 41 outputs the signal B1 at the "L" level.
It is composed of an OR gate 42 that outputs a signal B2 at an L" level, and a Nant gate 43 that outputs a luminance signal B at an "H" level when either of the output signals BI B2 of the OR gates 41 and 42 is at an "L" level. ing.

The brightness signal B output from the gate circuit 4 is input to the OR gate 6 along with the brightness signal Bm from the brightness signal memory circuit 5, and the output of the OR gate 6 is supplied to the cathode of the cathode ray tube 80 via the amplifier 7. There is.

Next, the operation of such a configuration will be explained with reference to the time chart shown in FIG.

First, the timing relationship between the vertical drive signal VD and the horizontal drive signal HD in the interlaced scanning method is as shown in FIG. 3 acd.

That is, in the second field scanning period F2, the falling edge of the horizontal synchronizing signal HD is synchronized with the rising timing of the vertical drive signal VD, and the falling edge of the horizontal synchronizing signal HD is synchronized with the rising timing of the vertical drive signal VD.
Then, the falling edge of the horizontal drive signal HD takes one hour (h;
horizontal scanning time).

Therefore, the vertical drive signal VD with such timing relationship
When the horizontal drive signal HD and horizontal drive signal HD are input to the field discrimination circuit 1, the one-shot multi 10 is triggered at the rising timing of the vertical drive signal VD, and the time width t shown by -<t<h as shown in FIG. One shot pulse W
In order to output P, the Nantes gate 11 outputs "L" only at the start timing of the first field scanning period F1.
A level output signal FID is output.

This signal FID is supplied as a cent signal to the flip-flop 12.

Therefore, the flip-flop 12 is in the cent state from the start timing of the first field scanning period F1 until the signal VD goes to the "L" level, and after the signal VD goes to the "L" level, the flip-flop 12 receives the signal FID from the Nant gate 11. It remains in the cent state until it is output.

As a result, a signal FLD1 as shown in FIG. 3e can be obtained from the cent output Q of the flip-flop.

That is, in the first field scanning period F1, the signal FLDI at the 'H' level can be obtained, and in the second field scanning period F2, the signal FLD1 at the 'L' level can be obtained.

On the other hand, in the decoding circuit 3, the NAND gate 30 outputs the pulse signal Pn indicating the n-th horizontal scanning period, and the pulse signal Pn indicating the n-th horizontal scanning period is output.
A pulse signal Pn+1 indicating the )th horizontal scanning period is output from the 7 lip flop processor 31.

Therefore, the output signals FLD1, Pn, and Pn+ of these field discrimination circuit 1 and decoding circuit 3.

is input to the gate circuit 4, the Nantes gate 43 outputs the "H" level luminance signal B during the (n+1)th horizontal scanning period of the first field scanning period, and the luminance signal B of the "H" level is output during the second field scanning period. In the n-th horizontal scanning period, the "H" level luminance signal B is output.

That is, the pulse signal Pn+1 indicating the (n+1)th horizontal scanning period is output as the luminance signal B only in the first field scanning period F1, and one pulse signal Pn
is the luminance signal B only in the second field scanning period F2.
is output as

As a result, as shown in FIG. 4, the horizontal scanning line indicated by Yn41 (Fl) lights up during the first field scanning period F1, and the horizontal scanning line indicated by Yn(F2) lights up during the second field scanning period F2.

That is, the horizontal line L can be displayed using only the two horizontal scanning lines closest to the boundary line between the pixels D1 and D2 arranged in the vertical direction.

As a result, such a horizontal line L becomes optimal for representing the boundary of the luminance signal from the pixel data memory.

In this embodiment, the vertical drive signal VD and the horizontal drive signal HD are used, but it goes without saying that a vertical synchronization signal and a horizontal synchronization signal may be used instead.

In this way, the present invention discriminates between the first field and the second field, and uses this discrimination signal to determine the nth field of the horizontal scanning line.
The signals indicating the th and (n+1)th numbers are alternately switched and output as a luminance signal.

Therefore, a horizontal line can be displayed using only the horizontal scanning line closest to the boundary line between two pixels arranged in the vertical direction, and the line becomes optimal as a line indicating the boundary between pixels.

[Brief explanation of drawings]

Fig. 1 is a diagram for explaining the drawbacks of the conventional horizontal line display, Fig. 2 is a circuit diagram showing an embodiment of the main part of the present invention, and Fig. 3 is a timing diagram for explaining the operation of the embodiment. chart,
FIG. 4 is a diagram showing horizontal line display in the embodiment. 1...Field discrimination circuit, 2...Horizontal scanning counter, 3...Decoding circuit, 4...
...Gate circuit.

Claims (1)

[Claims] In an interlaced scanning cathode ray tube display device that divides an 11-field display screen into pixel units and displays pixel memory data corresponding to each pixel as a luminance signal, a vertical synchronization signal and a horizontal synchronization signal are provided. a field determination circuit that determines the first or second field scanning period based on;
A horizontal scanning counter that counts horizontal synchronizing signals based on the vertical synchronizing signal, and decoding the output of this horizontal scanning counter to generate pulse signals of one horizontal scanning period at the n-th and (n+1)-th horizontal scanning timings, respectively. a decoding circuit for outputting, and a gate circuit for alternately switching and outputting pulse signals at the n-th and (n+1)-th horizontal scanning timings as luminance signals according to the output signal of the field discriminating circuit; A cathode ray tube display device that displays a boundary line between one pixel and one pixel.