KR890001308B1 - Crt monitor image size control circuit of a artificial sight system - Google Patents

Abstract

The circuit for adjusting the frame size of the monitor screen into twice or half one comprises a row counter (C) receiving a divided clock (A) of 19.661 MHz, a column counter (D) receiving horizontal synch. signal (B), a display selector (7) for selecting a full display clock (E) and a half display clock (F), a CRT controller (8), a video RAM (9), a CPU (10), a video ROM (11), an OR gate (12), and a CRT (G).

Description

CRT monitor screen size adjustment circuit of artificial visual system

1 is a block circuit diagram showing the main parts of the present invention.

FIG. 2 (a) shows a reduced CRT screen according to the present invention. FIG. 2 (b) shows an area where row and column values are set to explain a process in which the CRT screen of FIG. 2 (a) is reduced.

FIG. 3 (a) shows a waveform diagram in which a video signal and a horizontal synchronization signal are synthesized in the NTSC system.

FIG. 3 (b) shows the scan retrace time of the vertical synchronizing signal which is executed until the CRT frame is completed by two fields.

* Explanation of symbols for the main parts of the drawings

1,2,3: p. Counter 4,5,6: H counter

7: Screen 'display selector 8: CRT controller

9: Video RAM 10: Central Processing Unit (CPU)

11: Video ROM 12: Orgate

A: Frequency clock signal input terminal B: Horizontal synchronous signal input terminal

C: Low Counter D: Column Counter

E: Full Display Clock F: Half Display Clock

G: CRT monitor

The present invention can be applied to an artificial visual system, and more particularly, to a screen size adjusting circuit of a CRT monitor that can reduce or enlarge one screen to two screen sizes.

In general, the field used by adjusting the size of the screen is developing new video art by freely transforming the size of the screen in the field of video modulation. Especially, the video such as artificial visual system enables the work process in the automation system of industrial machines. This is very useful.

However, the conventional technology has a problem in that the screen size of the CRT monitor depends only on the program of the software so that the program must be changed every time the screen is resized. Accordingly, an object of the present invention is to allow a user to arbitrarily select a screen size as a monitor by applying a hardware screen adjustment circuit.

The screen size adjusting circuit of the CRT monitor according to the present invention includes a central processing unit (CPU) and a monitor, but is represented as one monitor by using a horizontal synchronous signal, a vertical synchronous signal, and a video signal produced from a closed circuit television (CCTV) camera. The program and the hardware may be combined to display the same type of screen with the same resolution so that the size of the screen may be adjusted, which will be more apparent when described in detail with reference to the accompanying drawings.

1 is a block diagram of an essential part of the present invention, in which a clock signal obtained by oscillating a frequency of 19,661 (MHZ) in a conventional oscillator (not shown in the figure) and re-segmenting (polarizing) the frequency to 4 clocks is A point (frequency). Clock signal input terminal).

In addition, the horizontal synchronizing signal and the vertical synchronizing signal of the north synchronizing signal are amplitude converted from a conventional closed circuit television (CCTV) camera and then the horizontal synchronizing signal and the vertical synchronizing signal by the RC unintegrating circuit in the synchronous separator not shown in the drawing. It is obtained by separating.

Under such conditions, the pulse (A) of the clock signal which has been frequency-reinforced from the above-described generator is applied to the input terminal of the low counter (C) consisting of the P-counters (1) (2) and (3), and The horizontal synchronous signal (B) separated in the conventional synchronous separator (not shown) is connected to the input terminal of the column counter (D) consisting of the H-counters (4) (5) and (6).

Then, the outputs of the low counter C and the column counter D are interconnected to be flip-flops, and then connected to the screen display selector 7.

The screen display selector 7 selects a full display clock (E) and a half display clock (F) to display the CRT screen. ) And then to the video RAM (9).

The video RAM 9 here stores a signal input from time to time.

The video RAM 9 and the video ROM 11 are connected to the central processing unit 10 and then connected to the input terminal G of the CRT monitor, which is not shown, through the or gate 12.

Referring to the operation and effect of the present invention configured as described above in detail.

In general, an image signal, a horizontal synchronization signal, and a vertical synchronization signal are required until the monitor interfaced with the CPU is displayed. Therefore, the video signal here can be obtained by the output of the video RAM 9 storing the data which changes every time. The horizontal synchronous signal and the vertical synchronous signal show the amplitude-modulated composite synchronous signal from the closed-loop television camera. By means of the RC value in the illustrated synchronous separator, it can be unintegrated and a horizontal synchronous signaled vertical synchronous signal can be obtained.

In addition, the divided clock signal applied to the A stage of FIG. 1 is a signal applied by oscillating a frequency of 19,661 (MHZ) in a general oscillator and then frequency-resetting to 4 clocks. do.

In each of the signals obtained in this manner, the frequency-divided divided clock signal A is first applied to the low counter C consisting of the P-counters 1, 2, and 3, and the horizontal synchronization signal. (B) is applied to the column counter D consisting of the H-counters 4, 5 and 6 at a constant high speed.

That is, in order to display the screen as shown in FIG. 2 (a), the XY coordinate value of the screen must be set. Therefore, the divided clock signal A and the horizontal synchronization signal B are set to the respective row and column counters C and D. It is applied and begins to count.

Then, when a signal continuously counted at each counter is applied to the screen display selector 9, the screen display selector indicates whether one screen is to be displayed full or only half by the program control signal of the central processing unit 10. It is decided in (7).

At this time, when the chip selection of the screen display selector 7 is selected by the central processing unit 10 as the full display (E), it is an interlaced scanning method similar to the display method of a general monitor and has a period twice as long as the half display clock signal. The clock signal calls 256 row, column value address from the video RAM 9 through the CRT controller 8, and when the horizontal synchronous signal comes in, it calls 256 row, column value address again. Since the operation is repeated until the synchronization signal is input, the row and column addresses of the video RAM 9 are increased so that the display of the screen becomes full.

In contrast, when the half display is selected, the above-described division clock signal A is applied to the low counter C after the half display is selected, and the low counter C gradually starts the counter. The column counter D also starts to counter the horizontal synchronization signal B gradually. When this is described with reference to FIGS. 2 (b) to 3 (a), one column having an access time of 10 (μS) is provided. When the horizontal synchronization signal is initially input from the column counter D, the access time corresponding to 53.5 (μS) of the video signal is terminated (determined by one scan line), and the second manual synchronization signal continues at a very high speed. It is input to the counter 4.

Then, the 2H counter 4 opens the gate of the low counter C counter 1 when the 64 horizontal synchronization signals are counted.

At this time, the P-counter 1 starts to count the divided clock signal A and completes counting 128 clocks. At the same time, the P-counter 2 of the next stage is operated, and the CRT controller 8 → video RAM ( 9) → Central Processing Unit 10 → Orgate 12 → Monitor G, and display from the 65th column P-counter 2 (Fig. 2 (b)) to 192 columns.

Then, after 256 picture elements have been scanned (refer to the p-counter 3 area in FIG. 2 (b)), the P-counter 3 is operated again to close the gate and display it. To stop.

This displays the 65th row and 65th column of the screen.

When the horizontal synchronizing signal (B) comes in again, this time the H-counter (5) of the column counter (D) receives the horizontal synchronizing signal (B) and up to the P-counter (1) (2) of the low counter (C). It operates as stated, and after 256 horizontal pixels have been scanned after displaying from the 66th on the screen, the P-counter 3 closes the gate and stops the display.

When the H-counter 5 of the column counter D completes the 128 horizontal synchronization signals due to the repeated operation as described above, the gate of the H-counter 6 is turned off at the same time as the low counter C is turned off. The 2H-counter 6, which is kept in the ON state, also counters the horizontal synchronizing signal, counts 16 or 32 horizontal synchronizing signals, and then selects the chip of the video ROM 11 having the character data stored therein. Then, the character data contained in the video ROM 11 is displayed on the CRT monitor G through the orate 12.

Therefore, as described above, the size of the screen using one monitor can be selected as full or half, so that two kinds of screens having the same resolution and resolution can be arbitrarily adjusted. Since the memory device of the central processing unit is applied to the display, it is very useful for video modulation fields such as an artificial visual system.

Claims (1)

The frequency division clock (A) of 19.661MH _{Z sets} the horizontal synchronization signal (B) to the T-counters 1,2,3 of the ROW counter (C) and the H-counters 4,5,6 of the column counter (D). Connect to the screen display selector (7) which selects the full display clock (E) and the half display clock (F), respectively, and connects the screen display selector (7) to the CRT controller (8) and the video RAM (9). , Video RAM (9) is the CRT monitor screen size adjustment circuit of the artificial visual system by connecting the central processing unit (10) and the video ROM (11) by connecting the orient (12) and the CRT monitor (C).

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