KR910004526B1 - Watchdog Timer Circuit - Google Patents

Abstract

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Description

Watchdog Timer Circuit

1 is a flow chart of pulses generated according to the normal status of the system.

2 is a circuit diagram according to the present invention.

3 is an operational waveform diagram of FIG. 2 according to the present invention;

* Explanation of symbols for main parts of the drawings

10: central processing unit 20: rectifier circuit

30: reference voltage generator 40: comparison signal generation and DC component blocking unit

50: reset control unit

The present invention relates to a watchdog timer circuit that detects when a central processing unit malfunctions and resets the central processing unit to restore normal operation. It relates to a watchdog timer circuit that can be.

In general, when the system program is executed by the central processing unit, if each program of the system is normally operated, a constant pulse signal is output through a predetermined terminal of the central processing unit as shown in the flowchart of FIG.

At this time, if an abnormality occurs in the central processing unit, the central processing unit does not output a constant pulse signal. In this case, a watchdog timer circuit is used to input a reset signal to the reset terminal of the central processing unit for program operation. Initialize

In the conventional watchdog timer circuit for realizing this, a monostable multivibrator or the like has been used, and thus, the circuit is complicated and the price increases.

Accordingly, an object of the present invention is to provide a watchdog timer circuit that can detect and reset a malfunction of a central processing unit at a low cost with a simple circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a flowchart of pulse generation generated according to whether a system is normal.

2 is a circuit diagram of the present invention, wherein 10 is a central processing unit for controlling the system as a whole by a program that outputs a constant pulse signal when a user normally performs a desired task, 20 is a capacitor C1, C2, It is composed of resistors (R3, R4) and diodes (D1) is a rectifier circuit unit for converting to a DC voltage having a constant level when the pulse signal of the central processing unit 10 is generated, 30 is a resistor (R1, R2) And a reference voltage generator for dividing an input voltage to generate a constant reference voltage, and 40 is an operational amplifier OP1, a capacitor C3, a resistor R5, and a diode D2. A comparison signal generation and a DC component blocking unit for blocking the DC component of the output signal by comparing the output voltage of the reference voltage and the reference voltage of the reference voltage generator 30, and 50 denotes a capacitor C4 and a resistor R6. , Consisting of transistor Q1, the comparison above The reset controller controls the reset stage RES of the central processing unit 10 according to the signal generation and the output signal of the DC component blocking unit 40.

3 is an operation waveform diagram according to FIG. 2, (a) is a reference voltage signal input to the non-inverting terminal (+) of the operational amplifier OP1, and (b) is an inverting terminal of the operational amplifier OP1. (C) is a comparison signal output from the operational amplifier OP1, and (d) blocks the DC component and the subcomponent (-) input to the base terminal of the transistor Q1. (E) is a waveform output from the collector terminal of the transistor Q1, and (f) is a waveform of a constant pulse signal output from the output terminal P1 of the central processing unit 10.

로 입력하여 상기 중앙처리장치(10)의 리세트를 해제한다.Hereinafter, the present invention will be described in detail with reference to FIGS. 1, 2, and 3. When the power is "on", the output terminal P1 of the central processing unit 10 transmits the "low" signal through the capacitor C1 and the diode D1 as shown in part (t1-t2) of FIG. 3f. Input the reverse terminal of (-). On the other hand, since the power supply VCC is converted into a reference voltage signal of the same level as 3a by the resistors R1 and R2 and is input to the non-inverting terminal + of the operational amplifier OP1, the operational amplifier OP1 is set to zero. Input the "high" comparison signal to the capacitor C3 as shown in part (t1-t2) of FIG. 3c. The "high" comparison signal input to the capacitor C3 is removed from the transistor Q1 through the resistor R5 as shown in part (t1-t2) of FIG. 3d after the negative component (−) is removed by the diode D2. Enter to the base end. Accordingly, the transistor Q1 is " on " and outputs a " high " signal at the collector stage as shown in part (t1-t2) of FIG. 3d. Therefore, the "high" signal output from the collector terminal of the transistor Q1 is delayed by a predetermined time as shown in part (t1-t2) of FIG. 3E by the charging time of the capacitor C4, and then the reprocessing of the CPU 10 is performed. Set terminal

To reset the central processing unit 10.

When the system is operating normally, the pulse output from the output terminal P1 of the central processing unit 10 as shown in (t2-t3) of FIG. 3f during the normal operation is transferred to the capacitor C1 and the resistor R3. The signal shaped by the differentiator made by the capacitor C1 and the resistor R3 is rectified by the half-wave rectifier circuit composed of the diode D1, the capacitor C2, and the resistor R4, and then the signal of FIG. Input it to the inverting terminal (-) of OP Amp as in (t2-t3) part.

로 입력하여 상기 중앙처리장치(10)는 정상적인 동작을 수행한다.On the other hand, since the power supply VCC is converted into a reference voltage signal equal to the third a degree by the resistors R1 and R2 and input to the non-inverting terminal + of the operational amplifier OP1, the operational amplifier OP1 is As shown in part (t2-t3) of FIG. 3C, a "low" comparison signal is input to the capacitor C3. The "low" comparison signal input to the capacitor C3 is a transistor (Q1) through the resistor (R5) as shown by the portion (t2-t3) of FIG. 3d after the negative component is removed by the diode D2. Enter the base of the. Therefore, the transistor Q1 is " off, " so that the "high" signal of the collector terminal is passed through the capacitor C4, as shown in part (t2-t3) of FIG.

The central processing unit 10 performs the normal operation.

At this time, if an abnormality occurs in the system and a pulse signal is not output through the output terminal P1 of the CPU 10 as shown in part (t3-t4) of FIG. 3f, the voltage charged in the capacitor C2 is a resistance ( Since it is discharged through R4), a "low" signal is input to the inverting terminal (-) of the operational amplifier OP1 as shown in part (t3-t4) of FIG. 3b and the non-inverting terminal (+) of the operational amplifier OP1. The reference voltage signal is input to the same as in FIG.

로 입력한다. 결과적으로 상기 중앙처리장치(10)는 소정의 리세트시간을 가진후에 정상동작 상태로 된다.Accordingly, the operational amplifier OP1 inputs a "high" comparison signal to the capacitor C3 as shown in part (t3-t4) of FIG. 3c, and the capacitor C3 inputs a DC component of the input "high" comparison signal. After removal, input to diode (D2). On the other hand, the diode (D2) is the base terminal of the transistor (Q1) through the resistor (R5) through a signal such as the (t3-t4) of the signal removed from the negative component (-) generated by the capacitor (C3) of Figure 3d Enter Therefore, the transistor Q1 is " on " and the " high " signal outputted from the collector terminal is reset for a predetermined time as shown in part (t3-t4) of FIG. 3e by the charging time of the capacitor C4. Reset terminal of central processing unit 10

Enter As a result, the CPU 10 enters a normal operation state after a predetermined reset time.

As described above, since the present invention can detect and reset the malfunction of the central processing unit, the cost of the product can be lowered by reducing the material cost by simplifying the circuit.

Claims (3)

A watchdog circuit having a central processing unit having a built-in pulse generation program, comprising: a rectifying circuit unit (20) for converting a DC signal having a predetermined level when a pulse signal of the central processing unit is input, After generating a comparison signal by comparing the reference voltage generator 30 generating a constant reference voltage with the output voltage of the rectifier circuit 20 and the reference voltage of the reference voltage generator 30, a DC signal of the comparison signal is generated. A reset for controlling the reset of the central processing unit 10 according to the comparison signal generation and DC component blocking unit 40 for blocking a signal, and the output signal of the means of the comparison signal generation and DC component blocking unit 40. Circuit comprising a control unit (50). The watchdog timer according to claim 1, wherein the rectifying circuit unit (20) comprises a shaping means for shaping the pulse signal of the central processing unit, and a half wave rectifying means for half-wave rectifying the signal shaping from the shaping means. Circuit. The operational amplifier of claim 1, wherein the comparison signal generation unit and the DC component blocking unit 40 generate a comparison signal by comparing the output voltage of the rectifying circuit unit 20 with the reference voltage of the reference voltage generator 30. OP1), a capacitor C3 for blocking the DC component of the comparison signal output from the operational amplifier OP1, and a diode D2 for blocking the subcomponent (−) generated by the capacitor C3. Watchdog timer circuit characterized in that.

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