JPS6067864A - Ac voltage detecting circuit - Google Patents

Abstract

PURPOSE:To detect the voltage drop of an AC power source or power failure at a high speed, by detecting the voltage drop or power failure of AC voltage by detecting that the output of an OFF delay timer comes to a low level. CONSTITUTION:Input voltage A is compared with a reference voltage level B by a voltage comparator 10 and the output F of an OFF delay timer 41 comes to a HI level at the rising of output voltage C when A=B while OFF delay of T/2 is similarly started at the falling thereof. When the output of an OR gate 36 is an HI level, resetting is performed and, when an LO level, integration begins. Output voltage N is compared with reference voltage P by a voltage comparator 34 and a Q-signal coming to HI output, wherein a time t1 from A 0 to A=L or a time t2 from A=L to A 0 is respectively longer than T/8, is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an AC voltage detection circuit that detects voltage drop or power outage of an AC power supply at high speed.

[Technical background of the invention and its problems] Conventionally, two methods have been used to detect AC voltage: (a) level detection of rectified and smoothed voltage (b) peak value detection of rectified ripple voltage. , (a) requires a filter with a large time constant for smoothing, so the detection time delay is large, and (b) has a ripple waveform that causes a maximum
There is a detection time delay of 2 cycles or 7 hours (T is the period of one cycle).

For example, FIG. 1 shows an AC voltage detection circuit using the method (b) above, in which the AC voltage AV is rectified by a full-wave rectifier 1,
Voltage comparator 1 as voltage signal A via attenuator 2
0 and is compared with a constant reference voltage level B, which corresponds to the rectified peak value when the AC voltage is normal, as shown in FIG. 2(a).

The voltage comparator 10 is turned on when A)B, and is off when A(B), so its output C is as shown in FIG. s (b).

The output C of the voltage comparator 10 is input to an off-delay timer 14 surrounded by a dotted line, which includes a voltage comparator 11, and is voltage-integrated by a capacitor 12.

As shown in FIG. 2(b), when the output C continues for 1/2 cycle or more, the voltage Di of the capacitor 12 exceeds the reference voltage E as shown in FIG. 2(c), and the voltage comparator 11 turns on. , the output F changes as shown in FIG. 2(d).

With this, a voltage drop in the AC voltage V is detected with a delay time of 1/2 cycle.

Note that the provision of a 2-cycle delay time is
This is because, as shown in Figures (a), (b), and (C), in normal conditions when the peak value of the rectified waveform matches the reference voltage level B, the output C has a maximum width of 1/2 cycle. .

In recent electronic devices, it is required to detect voltage drops and power outages of AC power supplies in a short time due to the need for memory backup, etc., but the above-mentioned conventional methods cannot satisfy this requirement.

[Object of the Invention] The present invention has an object to provide a high-speed AC voltage detection circuit that can detect voltage drops and power outages in AC voltage in a short time of less than a fraction of a cycle (for example, 1/8 cycle). There is.

[Summary of the Invention] The present invention compares a rectified voltage obtained by rectifying an alternating current voltage with a first reference voltage equal to the peak value during normal operation, and outputs an output when the instantaneous value of the rectified voltage is equal to or higher than the first reference voltage. A 1/2 cycle off-delay timer with a reset terminal set to HI level, and the rectified voltage is compared every half cycle with a second reference voltage lower than the first reference voltage, and the instantaneous value of the rectified voltage is determined. a low voltage comparator circuit that resets the off-delay timer when the period when the voltage is lower than the second reference voltage is a fraction of a cycle (for example, 1/8 cycle) or more; and the H value of the rectified voltage is close to zero. A zero voltage comparator circuit is provided which resets the off-delay timer when the period exceeds a predetermined time Δ, and when the output of the off-delay timer reaches the LO level, a drop in AC voltage or a power outage is detected. This is an AC voltage detection circuit that can detect voltage drops and power outages in AC power supplies at high speed.

[Embodiment of the Invention] An embodiment of the present invention is shown in FIG. FIG. 6 is a time chart showing the operation of the present invention.

In FIG. 4, the input AC voltage AV is input to the attenuator 2 via the full-wave rectifier 1, and its output A11-1 is a reference voltage B obtained by dividing the voltage V with the resistors 3 and 4 in the voltage comparator 10. The output C is input to the off-delay timer 41.

Furthermore, the output chamber press-in is compared by voltage comparators 31 and 33 with a reference voltage G obtained by resistors 21 and 22 and a reference voltage G obtained by resistors 26 and 27, respectively. -1. M is input to OR gate 36.

The output of the OR gate 36 is input to an integrating circuit consisting of a resistor and a capacitor 38, and its output voltage N is input to a voltage comparator 3.
4, the output Q of the voltage comparator 34 is compared with the reference voltage P obtained by the resistors 29 and 30, and the output Q of the voltage comparator 34 is inputted to the reset terminal of the off-delay timer 41 via the diode 40.

Similarly, the output H of the voltage comparator 31 is input to the inverting amplifier 35, and its output is connected to the resistor 23. The capacitor 37 (= is input to the integrating circuit, and its output Il′i voltage comparator 32
The output Kid of the voltage comparator 32 is compared with the reference voltage J obtained by the resistors 24 and 25 and is inputted to the reset terminal of the off-delay timer 41 via the diode 39.

FIG. 5 is a time chart showing the operation of the off-delay timer.

Next, the present invention will be explained in detail using the time chart shown in FIG.

As shown in FIG. 6, the input chamber press-in is compared with the reference voltage level B by the voltage comparator IO, and when A≧B, the output voltage C
At the rising edge of F?, the output of the off-delay timer 41 is F? 'iHI
The level and fx also activate the T/2 off-delay at the falling edge.

Furthermore, the voltage A is compared with a reference voltage G set to a very low level by a voltage comparator 31 and a reference voltage R by a voltage comparator 33, and their respective outputs H and M are
It is logically summed by R gate 36, and its output is connected to resistor 28. The start of integration and reset of the integrating circuit are controlled by the capacitor 38 (==), and the output voltage N is obtained.

That is, when the output of the OR gate 36 is at the Hl level, it is reset and time integration of the LO level starts.

This output voltage N is compared with the reference voltage P obtained by the resistor 29.30 by the pressure comparator 34, and the time tl from A80 to A=L or the time t2 from A=L to Aki0 is determined. Each generates a Q signal that becomes a HI output when it is longer than T/8.

That is, resistor 28. The charging time constant of the phase dividing circuit by the capacitor 38 is determined by the charging voltage after T/8 hours by the resistor 29.
, : If the voltage is selected so that it almost reaches the voltage P obtained by dividing the voltage V by 30, the detection time delay j is approximately T/
It becomes 8.

Further, the output signal I of the voltage comparator 31 is inverted by an inverting amplifier 35, and its output is used to connect the resistor 23. capacitor 3
7 controls the integration start and reset of the integrator circuit to obtain the output (■).

This output I is compared with a reference voltage J obtained by resistors 24 and 25 in a voltage comparator 32, and a HI output K is generated when the period A is longer than Δt.

Resistor 23. The charging time constant of the integrating circuit by the capacitor 37 is also determined by the calculated value of the pulse width t8 of the output H obtained by the voltage comparator 31.
It is important to set the voltage so that it does not reach the voltage J obtained by dividing the voltage, but even if the reference voltage G of the voltage comparator 310 is set to a very low level, the output pulse H will be increased by +V, so % ts << tx, 1 is obtained, and the detection time delay Δt can also be set to Δt << T/8.

The outputs of the voltage comparators 32 and 34, Q, are logically summed by diodes 39 and 40, and when they rise to HI level, the off-delay timer 41 is reset, and the output F
is reset to LO level only when is at HI level.

This reduces the voltage drop to a maximum of T/8. A power outage can be detected with a detection time delay of maximum Δt.

As shown in the cut figure 7, XB = A X sn 22
．． Add a voltage comparator 51.52 with a standard value of 5° + X4 = A, (22, 360°) X T =
T/16 or if the period of Xa<A<Xz is A
=X3, but if A=X2 is longer than T/16, or if the period of X2 < A < X4 is A=x
By configuring the off-delay timer to be reset when the off-delay timer is longer than T/16 as calculated from A=X4, it becomes possible to detect a voltage drop with a maximum detection time delay of T/16.

- FIG. 8 is a time chart showing the above operation. , S2 is a switch for starting integration and resetting the RCf1 circuit. [Effects of the Invention] As explained above, according to the present invention, the voltage drop of the AC voltage can be reduced to 1/8 cycle or less (reduced (is not necessary). by 1/16
This provides a high-speed AC voltage detection circuit that can detect voltages in less than one cycle).

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional AC voltage detection circuit.
Figures 2 and M3 are time charts showing the operation;
Fig. 4 is a circuit diagram showing one embodiment of the present invention, and Fig. 5 is a circuit diagram showing an embodiment of the present invention.
6 is a time chart showing the operation of the off-delay timer in FIG. 4, FIG. 7 is a circuit diagram showing another embodiment of the present invention, and FIG.
5 is a time chart showing the operation shown in the figure. l... Full wave rectifier 2... Attenuator 10, l
], 31-34.51-54...voltage comparator 14
, 41... Off-delay timer 35/inverting amplifier
36...OR gate agent Patent attorney Yoshiaki Inomata (and 1 other person) Figure 1 Figure 2 Figure 4- Figure 4/ Figure 5 OR'EMT'

Claims (1)

[Claims] Comes with a reset terminal that compares the full-wave rectified AC voltage with a first reference voltage that is equal to the normal peak value, and sets the output to HI level when the instantaneous value of the rectified voltage is greater than or equal to the first reference voltage. A 1/2 cycle off-delay timer compares the rectified voltage with a second reference voltage lower than the first reference voltage every half cycle, and determines a period during which the instantaneous value of the rectified voltage is lower than the second reference voltage. A low voltage comparator circuit that resets the off-delay timer when it is longer than a fraction of a cycle, and a zero voltage that resets the on-delay timer when the period during which the instantaneous value of the rectified voltage is near zero is longer than a predetermined time △. An AC voltage detection circuit comprising a comparison circuit and detecting a drop in AC voltage or a power outage when the output of the off-delay timer returns to LO level.