KR890015104A - Watchdog Timer Circuit - Google Patents

Watchdog Timer Circuit Download PDF

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Publication number
KR890015104A
KR890015104A KR1019880003567A KR880003567A KR890015104A KR 890015104 A KR890015104 A KR 890015104A KR 1019880003567 A KR1019880003567 A KR 1019880003567A KR 880003567 A KR880003567 A KR 880003567A KR 890015104 A KR890015104 A KR 890015104A
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KR
South Korea
Prior art keywords
unit
comparison signal
reference voltage
component
blocking
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Application number
KR1019880003567A
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Korean (ko)
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KR910004526B1 (en
Inventor
신금호
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강진구
삼성반도체통신 주식회사
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Priority to KR1019880003567A priority Critical patent/KR910004526B1/en
Publication of KR890015104A publication Critical patent/KR890015104A/en
Application granted granted Critical
Publication of KR910004526B1 publication Critical patent/KR910004526B1/en

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Abstract

내용 없음.No content.

Description

워치독 타이머회로Watchdog Timer Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 회로도.2 is a circuit diagram according to the present invention.

제3도는 본 발명에 따른 제2도의 동작 파형도.3 is an operational waveform diagram of FIG. 2 according to the present invention;

Claims (3)

펄스발생 프로그램이 내장된 중앙처리장치를 구비한 워치독 회로에 있어서, 상기 중앙처리장치의 펄스신호가 입력될시 일정한 레벨을 가지는 직류전압으로 변환하는 정류회로부(20)와, 입력전원을 분압하여 일정한 기준전압을 발생하는 기준전압 발생부(30)와, 상기 정류회로부(20)출력전압과 기준전압 발생부(30)의 기준전압을 비교하여 비교신호를 생성한후 상기 비교신호의 직류성분을 차단하는 비교신호생성 및 직류성분 차단부(40)와, 상기 비교신호생성 및 직류성분 차단부(40)의 수단의 출력신호에 따라 상기 중앙처리장치(10)의 리세트를 제어하는 리세트 제어부(50)로 구성됨을 특징으로 하는 회로.A watchdog circuit having a central processing unit having a built-in pulse generation program, comprising: a rectifying circuit unit 20 for converting a DC signal having a predetermined level when a pulse signal of the central processing unit is inputted, and by dividing an input power source; Comparing the reference voltage generator 30 generating a constant reference voltage, the output voltage of the rectifier circuit 20 and the reference voltage of the reference voltage generator 30 generates a comparison signal, and then calculates a DC component of the comparison signal. A reset control unit for controlling the reset of the CPU 10 according to the comparison signal generation and DC component blocking unit 40 to cut off and the output signal of the means of the comparison signal generation and DC component blocking unit 40. Circuit, characterized in that it comprises (50). 제1항에 있어서, 상기 정류회로부(20)가 상기 중앙처리장치의 펄스신호를 정형하는 정형수단과, 상기 정형수단에서 정형된 신호를 반파정류하는 반파정류수단으로 구성됨을 특징으로 하는 워치독 타이머회로.The watchdog timer according to claim 1, wherein the rectifying circuit unit (20) comprises a shaping means for shaping a pulse signal of the central processing unit and a half-wave rectifying means for half-wave rectifying the signal shaped by the shaping means. Circuit. 제 1항에 있어서, 상기 비교신호생성 및 직류성분 차단부(40)가 상기 정류회로부(20)의 출력전압과 기준전압 발생부(30)의 기준전압을 비교하여 비교신호를 생성하는 연산증폭기(OP1)와, 상기 연산증폭기(OP1)에서 출력되는 비교신호의 직류성분을 차단하는 캐패시터(C3)와, 상기 캐패서터(C3)에 의해 발생하는 부성분(-)을 차단하는 다이오드(D2)로 구성됨을 특징으로 하는 워치독 타이머회로.The operational amplifier of claim 1, wherein the comparison signal generation unit and the DC component blocking unit 40 generate a comparison signal by comparing the output voltage of the rectifying circuit unit 20 with the reference voltage of the reference voltage generator 30. OP1), a capacitor C3 blocking the DC component of the comparison signal output from the operational amplifier OP1, and a diode D2 blocking the subcomponent (-) generated by the capacitor C3. Watchdog timer circuit, characterized in that configured. ※참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: This is to be disclosed based on the first application. 제1항에 있어서, 상기 비교신호생성 및 직류성분 차단부(40)가 상기 정류회로부(20)의 출력전압과 기준전압 발생부(30)의 기준전압을 비교하여 비교신호를 생성하는 연산증폭기(OP1)와, 상기 연산증폭기(OP1)에서 출력되는 비교신호의 직류성분을 차단하는 캐패시터(C3)와 상기 캐패시터(C3)에 의해 발생하는 부성분(-)을 차단하는 다이오드(D2)로 구성됨을 특징으로 하는 워치독 타이머회로.The operational amplifier of claim 1, wherein the comparison signal generation unit and the DC component blocking unit 40 generate a comparison signal by comparing the output voltage of the rectifying circuit unit 20 with the reference voltage of the reference voltage generator 30. OP1), a capacitor (C3) for blocking the DC component of the comparison signal output from the operational amplifier (OP1) and a diode (D2) for blocking the negative component (-) generated by the capacitor (C3) Watchdog timer circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880003567A 1988-03-31 1988-03-31 Watchdog Timer Circuit KR910004526B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880003567A KR910004526B1 (en) 1988-03-31 1988-03-31 Watchdog Timer Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880003567A KR910004526B1 (en) 1988-03-31 1988-03-31 Watchdog Timer Circuit

Publications (2)

Publication Number Publication Date
KR890015104A true KR890015104A (en) 1989-10-28
KR910004526B1 KR910004526B1 (en) 1991-07-05

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Application Number Title Priority Date Filing Date
KR1019880003567A KR910004526B1 (en) 1988-03-31 1988-03-31 Watchdog Timer Circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020013800A (en) * 2000-08-14 2002-02-21 니시가키 코지 Frequency determination circuit for a data processing unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020013800A (en) * 2000-08-14 2002-02-21 니시가키 코지 Frequency determination circuit for a data processing unit

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Publication number Publication date
KR910004526B1 (en) 1991-07-05

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