KR910000212Y1 - Timer circuitry using hand gate - Google Patents
Timer circuitry using hand gate Download PDFInfo
- Publication number
- KR910000212Y1 KR910000212Y1 KR2019860018557U KR860018557U KR910000212Y1 KR 910000212 Y1 KR910000212 Y1 KR 910000212Y1 KR 2019860018557 U KR2019860018557 U KR 2019860018557U KR 860018557 U KR860018557 U KR 860018557U KR 910000212 Y1 KR910000212 Y1 KR 910000212Y1
- Authority
- KR
- South Korea
- Prior art keywords
- nand gate
- logic control
- circuit
- control circuit
- resistor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.
제2도는 전원인가시 각 부분의 상태도.2 is a state diagram of each part when the power is applied.
제3도는 주요부분에 대한 부호의 설명.3 is a description of symbols for the main parts.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
SW1: 전원스위치 4 : 로직 콘트롤회로SW 1 : power switch 4: logic control circuit
1,2 : 지연회로 T1: 스위칭 트랜지스터1,2: delay circuits T 1: the switching transistor
G1,G2: 낸드게이트 3 : 방전회로G 1 , G 2 : NAND gate 3: Discharge circuit
본고안은 로직콘트롤 회로에 전원이 입력되었을 때 상기 입력된 전원이 일정시간이 경과한후 로직콘트롤 회로에 미리 설정된 시간만큼 전원이 공급되도록 되어있는 낸드게이트를 이용한 타이머회로에 관한 것이다.The present invention relates to a timer circuit using a NAND gate such that when a power is input to a logic control circuit, the input power is supplied to the logic control circuit for a predetermined time after a predetermined time has elapsed.
일반적으로 로직콘트롤 회로는 논리소자를 사용하였기 때문에 전원공급과 동시에 로직콘트롤 회로가 동작하게 되면 노이즈로 인해 로직콘트롤 회로는 오동작을 하게 되므로, 로직 콘트롤 회로에서는 전원이 인가된후 일정한 전압이 될 때까지 전원의 공급을 지연시켜 주는 타이머가 필요하다.In general, the logic control circuit uses a logic element, so if the logic control circuit operates at the same time as the power supply, the logic control circuit malfunctions due to noise. In the logic control circuit, until the voltage reaches a constant voltage after the power is applied. A timer is needed to delay the supply of power.
종래의 기계식이나 전자식 타이머들은 단지 설정된 시간만큼만 전원의 공급을 지연시켜주는 단순한 기능밖에 수행을 하지 못하므로 로직콘트롤 회로에는 사용할 수가 없었다.Conventional mechanical or electronic timers cannot be used in logic control circuits because they only perform a simple function of delaying the supply of power by a set time.
본고안은 이러한 점을 감안하여 안출한 것으로 논리소자인 낸드게이트의 전후단에 각각 저항과 콘덴서를 이용한 충방전 회로를 구비시켜, 스위칭 트랜지스터로 로직콘트롤 회로를 제어함으로서, 전원이 공급되면, 이 전원을 일정시간 지연시켜 정전압을 만든후에 설정된 시간동안 전원이 공급되도록 하여 갑작스런 전원의 인가로 인해 로직콘트롤 회로에서 발새하는 오동작을 방지하는데 본고안의 목적이 있다.The present invention has been devised in view of this point, and the charge and discharge circuit using resistors and capacitors are provided at the front and rear ends of the NAND gate, which is a logic element, and the logic control circuit is controlled by a switching transistor. The purpose of this paper is to prevent the malfunction occurring in the logic control circuit due to the sudden application of power by supplying the power for the set time after making the constant voltage by delaying the fixed time.
첨부된 도면에 의거하여 본고안의 구성 및 작용효과는 상세히 설명하면 다음과 같다.On the basis of the accompanying drawings will be described in detail the configuration and operation effects of the present invention.
제1도는 본고안의 회로도인데, 전원이 저항(R2,R3,R4,R7)을 통해 낸드게이트(G1,G2)의 단자(A1,B1,A2)와 접속되어 있고, 낸드게이트(G2)의 다른 한쪽단자(B2)는 낸드게이트(T1)의 출력단자(Q1)로부터 저항(R5)과 콘덴서(C2)의 지연회로(2)와 콘덴서(C2)와 저항(R6)의 방전회로(3)와 접속되어 있고, 낸드 게이트(G2)의 출력(Q2)은 베이스와 콜렉터가 로직콘트롤 회로와 연결된 트랜지스터(T1)의 에미터와 접속시켜 구성한 회로이다.1 is a circuit diagram of the present invention, the power supply is connected to the terminals A 1 , B 1 , A 2 of the NAND gates G 1 , G 2 through the resistors R 2 , R 3 , R 4 , R 7 . The other terminal B 2 of the NAND gate G 2 is connected to the delay circuit 2 of the resistor R 5 and the capacitor C 2 and the capacitor from the output terminal Q 1 of the NAND gate T 1 . (C 2) and the emitter of the discharge circuit 3 is connected, and a NAND gate (G 2), the output (Q 2) is a transistor (T 1) a base and a collector connected to the logic control circuit of a resistor (R 6) It is a circuit constructed by connecting to a computer.
스위치(SW1)가 개방상태에 있을때는 낸드게이트(G1)의 입력단자(A1,B1)가 모두 고전위상태에 있으므로, 출력(Q1)은 저전위상태가 된다.When the switch SW 1 is in the open state, since the input terminals A 1 and B 1 of the NAND gate G 1 are both at high potential, the output Q 1 is at a low potential state.
따라서 낸드게이트(G2)의 입력단자(A2,B2)는 각기 고전위, 저전위가 되고, 출력(Q3)은 고전위상태가 되므로 트랜지스터(T1)는 동작하지 않아, 로직콘트롤 회로는 구동되지 않는다.Accordingly, since the input terminals A 2 and B 2 of the NAND gate G 2 become high potential and low potential, respectively, and the output Q 3 becomes a high potential state, the transistor T 1 does not operate and the logic control is performed. The circuit is not driven.
스위치(SW1)를 연결하면 낸드게이트(G1)의 A1단자는 고전위 상태를 유지하며, B1단자는 콘덴서(C1)과 저항(R2)으로 구성된 지연회로 때문에 지연시간(t1)동안 저전위 상태에 있게 되므로, 출력(Q1)은 고전위 상태가 되나, 저항(R5)과 콘덴서(C2)로 구성된 지연회로에 의하여 t2라는 시간동안 낸드 게이트(G2)의 B2단자는 저전위 상태에 있게 되므로, 출력(Q2)은 고전위 상태에 있게 되어, 트랜지스터(T1)가 동작하지 않으므로 로직콘트롤 회로는 구동되지 못하게 된다.When the switch SW 1 is connected, the A 1 terminal of the NAND gate G 1 maintains a high potential state, and the B 1 terminal has a delay time t due to a delay circuit composed of a capacitor C 1 and a resistor R 2 . 1) NAND gates for, so to be in the low potential state, the output (Q 1) is termed a high potential state, a resistance (R 5) and a capacitor (C 2) t 2 of time by a delay circuit composed of for (G 2) Since the B 2 terminal of is in the low potential state, the output Q 2 is in the high potential state, and the logic control circuit is not driven because the transistor T 1 is not operated.
이때(1) 지연회로와 (2)지연회로는 동시에 충전되기 때문에 지연시간 t1=t2가 된다.At this time, since the delay circuit (1) and the delay circuit (2) are simultaneously charged, the delay time t 1 = t 2 is obtained.
t1(=t2)의 시간이 경과한 후에는 낸드 게이트(G1)의 입력단자(A1,B1)가 모두 고전위 상태에 있게 되므로, 출력(Q1)은 저전위가 되나, 콘덴서(C2)와 저항(R6)으로 구성된 방전회로에 의하여 t3라는 방전시간 동안 낸드 게이트(G2)의 B2단자는 고전위 상태를 유지하므로, 출력(Q2)은 저전위 상태가 되어 트랜지스터(T1)가 턴온되어 로직콘트롤 회로를 구동시킨다.After the time t 1 (= t 2 ) elapses, the input terminals A 1 and B 1 of the NAND gate G 1 are in a high potential state, and thus the output Q 1 becomes low potential. Since the B 2 terminal of the NAND gate G 2 maintains a high potential state during a discharge time of t 3 by a discharge circuit composed of a capacitor C 2 and a resistor R 6 , the output Q 2 is in a low potential state. Transistor T 1 is turned on to drive the logic control circuit.
제2도는 시간에 따른 낸드게이트(G1,G2) 및 출력(Q1,Q2)의 상태를 도시한 것인데, t1(t2)의 시간이 경과한 후에 낸드 게이트(G2)의 출력이 방전시간(T3)만큼 저전위 상태에 있게 되므로, 트랜지스터(T1)을 도통시켜, 로직콘트롤 회로를 구동시킨 다는 것을 도식적으로 나타내고 있다.Second time NAND gate in accordance with the turn (G 1, G 2) and the output geotinde showing a state of (Q 1, Q 2), the t 1 (t 2) a NAND gate (G 2) after a lapse of time of Since the output is in the low potential state by the discharge time T 3 , the transistor T 1 is turned on to drive the logic control circuit.
상기와 같이 본고안은 스위치(SW1) 콘덴서(C1)와 저항(R2)로 구성된 자연회로를 구비하여 입력된 전원을 일정시간(T1)동안 지연시킨 다음 낸드게이트(G2) 출력(Q2)의 저전위 상태에 의해 트랜지스터(T1)가 턴온되어 로직콘트롤 회로를 구동시킴으로서, 일반 기계식 및 전자식 타이머를 로직 콘트롤 회로에 사용할 때 발생하는 오동작을 방지할수 있다는 장점이 있다.As described above, the present invention includes a natural circuit composed of a switch (SW 1 ) capacitor (C 1 ) and a resistor (R 2 ) to delay the input power for a predetermined time (T 1 ) and then output the NAND gate (G 2 ). Since the transistor T 1 is turned on by the low potential state of Q 2 to drive the logic control circuit, there is an advantage that a malfunction occurs when a general mechanical and electronic timer is used in the logic control circuit.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860018557U KR910000212Y1 (en) | 1986-11-27 | 1986-11-27 | Timer circuitry using hand gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860018557U KR910000212Y1 (en) | 1986-11-27 | 1986-11-27 | Timer circuitry using hand gate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR880010874U KR880010874U (en) | 1988-07-28 |
| KR910000212Y1 true KR910000212Y1 (en) | 1991-01-18 |
Family
ID=19257402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019860018557U KR910000212Y1 (en) | 1986-11-27 | 1986-11-27 | Timer circuitry using hand gate |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR910000212Y1 (en) |
-
1986
- 1986-11-27 KR KR2019860018557U patent/KR910000212Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR880010874U (en) | 1988-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3824447A (en) | Booster circuit | |
| KR910000212Y1 (en) | Timer circuitry using hand gate | |
| JP3261151B2 (en) | Reset signal generation circuit device | |
| US3818249A (en) | Pulse generating circuit | |
| US4672233A (en) | Controller with dual function switch | |
| JPS592427A (en) | Connecting device with delay unit | |
| KR860002292Y1 (en) | Timer circuit using nor-gate | |
| KR890003753Y1 (en) | Automatic reset circuit in micro computer | |
| KR910006697Y1 (en) | Mode signal delay circuit for mode setting circuit | |
| KR920004509Y1 (en) | Reset circuit using switching elements | |
| JPH082894Y2 (en) | Power switch circuit | |
| KR960001076B1 (en) | Oscillation inducing circuit | |
| SU1499454A1 (en) | Device for protection against contact chatter | |
| FR2312396A1 (en) | Electric wind screen washer pump energy supply - is of solid state type with logic elements giving some programmed alternative of operation | |
| KR880003433Y1 (en) | Starting control circuit | |
| JPH09261024A (en) | Switching circuit | |
| KR880003261Y1 (en) | Cmos reset circuit | |
| SU907805A1 (en) | And-or-and/and-or-and-not element | |
| JPS57112135A (en) | Mos type analogue switch integrated circuit | |
| JPH05119871A (en) | Resetting circuit | |
| KR950007461B1 (en) | Pulse generated circuit | |
| CA1174300A (en) | Rc oscillator circuit | |
| JPS647701B2 (en) | ||
| SU1034190A1 (en) | Device for set logical elements in initial state when voltage supply failure | |
| JPH02294224A (en) | Residual electric charge discharging circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| REGI | Registration of establishment | ||
| FPAY | Annual fee payment |
Payment date: 19981231 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |