JPS647701B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to power supply timer circuits.

So-called power supply timer circuits are widely used in small electrical devices such as electronic desktop calculators, and their function is to keep the device operating for a predetermined period of time after the power is turned on and the device is operated. If not, the device will be automatically rendered inoperable.

The present invention was also made as part of the development of this type of power supply timer circuit, and includes a first transistor inserted between a power supply and a load circuit to open and close an electric circuit, and a first transistor that is charged and discharged in accordance with the operation of a power switch. The main components are a capacitor that controls the first transistor, and a second transistor that controls the first transistor together with the capacitor in response to a response signal from the load circuit, forming a simple power supply timer circuit.

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the present invention.
is a power supply, and its ten poles are connected to one end of the load circuit L via the emitter and collector of the transistor _Tr1 , and its one pole is connected to the other end of the load circuit L. The ten poles and one pole of power supply E are also the power switch SW.
The switching contact of the power switch SW is connected to the emitter-collector of the transistor Tr ₂ and to the base of the transistor Tr ₁ via the low resistor R ₂ . The base of the transistor Tr ₁ is connected to the emitter via a resistor R ₁ . Collector of transistor Tr ₂
A capacitor C is connected across the emitter, the collector is connected to the ten poles of the power source E via a diode _D1 , and the base is connected to the responsive signal terminal of the load circuit L.

In this circuit, when the power switch SW is switched from off to on, a capacitor C is connected across the power supply E via resistors R ₁ and R ₂ and the power switch SW, and the capacitor C is charged. A voltage drop across the resistor _R1 due to this charging current applies a bias between the emitter and base of the transistor _Tr1 , turning on the transistor _Tr1 and supplying power to the load circuit L via its emitter and collector. The load circuit L provides a response signal to the base of the transistor Tr ₂ when power is supplied. This turns on the transistor Tr ₂ and forms a current path for the base current of the transistor Tr ₁ . By turning on the transistor _Tr2 , the charge in the capacitor C becomes discharged.

When the load circuit L finishes the predetermined operation, it stops sending out the response signal to the base of the transistor Tr ₂ , so the transistor Tr ₂ is turned off. At this time, the base current of the transistor _Tr1 flows into the capacitor C. Then, charging is performed until the charging voltage of the capacitor C becomes approximately equal to the power supply voltage, and during this time, the transistor Tr ₁ continues to be in the on state and then turned off. This is a power supply stop due to timer operation, and the timer time is determined by the time constant of resistor _R2 and capacitor C.

To supply power again, the power switch SW should be turned off once to discharge the charge in the capacitor C, and then turned on. As a result, power is supplied by the same operation as described above.

On the other hand, when the on-state power switch SW is turned off, transistor Tr ₂ is immediately turned off, and capacitor C is short-circuited via diode D, so the base current of transistor Tr ₁ stops flowing, and power supply from the power supply stops. do.

FIG. 2 is a time chart for explaining the operation of the embodiment shown in FIG. 1. When the power switch SW is turned on, transistors Tr ₁ and Tr ₂ are turned on, a load responsive signal is generated, and the transistor Tr ₂ is turned on. The collector potential becomes 0. Then, when the load responsive signal disappears, the transistor Tr ₂ is turned off, the collector potential of the transistor Tr ₂ rises, and after the timer time T has elapsed, the transistor Tr ₁ is turned off and power supply is stopped. Then, when the power switch SW is turned off, the collector potential of the transistor _Tr2 instantaneously rises to the power supply voltage E.

In the above embodiment, the circuit is constructed using bipolar transistors, but it may also be constructed using field effect transistors.

As described above, the present invention has a circuit configuration using a first transistor that opens and closes a power supply path to a load circuit, a capacitor that controls this first transistor according to power switch operation and load response, and a second transistor. Therefore, it is possible to provide a power supply timer circuit with a simple configuration.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a time chart for explaining the circuit operation of FIG. 1. Tr...transistor, SW...power switch, E...
power supply.

Claims (1)

[Claims] 1. An electric circuit is formed by a power switch that switches between ten poles and one pole of the power supply, a first transistor inserted between the power supply and the load circuit to open and close it, and the on operation of the power switch. Charging is carried out according to a predetermined time constant, and a capacitor that turns on the first transistor during the charging operation is connected in parallel to this capacitor and turns on when a response signal is applied from the load circuit. A power timer circuit comprising: a second transistor that turns on the first transistor; and a diode that forms a discharge path for the capacitor together with the power switch when the power switch is turned off.