KR900012934U - Cpu보드상의 이중 포트 기억장치 회로 - Google Patents

Cpu보드상의 이중 포트 기억장치 회로

Info

Publication number
KR900012934U
KR900012934U KR2019880022110U KR880022110U KR900012934U KR 900012934 U KR900012934 U KR 900012934U KR 2019880022110 U KR2019880022110 U KR 2019880022110U KR 880022110 U KR880022110 U KR 880022110U KR 900012934 U KR900012934 U KR 900012934U
Authority
KR
South Korea
Prior art keywords
storage circuit
dual port
cpu board
port storage
cpu
Prior art date
Application number
KR2019880022110U
Other languages
English (en)
Other versions
KR940002595Y1 (ko
Inventor
인희식
Original Assignee
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 금성사 filed Critical 주식회사 금성사
Priority to KR2019880022110U priority Critical patent/KR940002595Y1/ko
Publication of KR900012934U publication Critical patent/KR900012934U/ko
Application granted granted Critical
Publication of KR940002595Y1 publication Critical patent/KR940002595Y1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
KR2019880022110U 1988-12-30 1988-12-30 Cpu보드상의 이중 포트 기억장치 회로 KR940002595Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019880022110U KR940002595Y1 (ko) 1988-12-30 1988-12-30 Cpu보드상의 이중 포트 기억장치 회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019880022110U KR940002595Y1 (ko) 1988-12-30 1988-12-30 Cpu보드상의 이중 포트 기억장치 회로

Publications (2)

Publication Number Publication Date
KR900012934U true KR900012934U (ko) 1990-07-04
KR940002595Y1 KR940002595Y1 (ko) 1994-04-21

Family

ID=19282753

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019880022110U KR940002595Y1 (ko) 1988-12-30 1988-12-30 Cpu보드상의 이중 포트 기억장치 회로

Country Status (1)

Country Link
KR (1) KR940002595Y1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419682B1 (ko) * 1999-01-27 2004-02-21 마츠시타 덴끼 산교 가부시키가이샤 액세스 제어 장치 및 액세스 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419682B1 (ko) * 1999-01-27 2004-02-21 마츠시타 덴끼 산교 가부시키가이샤 액세스 제어 장치 및 액세스 방법

Also Published As

Publication number Publication date
KR940002595Y1 (ko) 1994-04-21

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Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
LAPS Lapse due to unpaid annual fee