KR900011155A - 전원공급전압 변동에 대해 안정한 씨모스 입력 버퍼회로 - Google Patents

전원공급전압 변동에 대해 안정한 씨모스 입력 버퍼회로

Info

Publication number
KR900011155A
KR900011155A KR1019880017051A KR880017051A KR900011155A KR 900011155 A KR900011155 A KR 900011155A KR 1019880017051 A KR1019880017051 A KR 1019880017051A KR 880017051 A KR880017051 A KR 880017051A KR 900011155 A KR900011155 A KR 900011155A
Authority
KR
South Korea
Prior art keywords
power supply
supply voltage
buffer circuit
input buffer
voltage fluctuation
Prior art date
Application number
KR1019880017051A
Other languages
English (en)
Other versions
KR910007785B1 (ko
Inventor
김병윤
박용보
정태성
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR1019880017051A priority Critical patent/KR910007785B1/ko
Priority to US07/289,731 priority patent/US4890051A/en
Priority to JP63328076A priority patent/JPH088481B2/ja
Priority to NL8903056A priority patent/NL191426C/xx
Publication of KR900011155A publication Critical patent/KR900011155A/ko
Application granted granted Critical
Publication of KR910007785B1 publication Critical patent/KR910007785B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Radar, Positioning & Navigation (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
KR1019880017051A 1988-12-20 1988-12-20 전원공급전압 변동에 대해 안정한 씨모스 입력 버퍼회로 KR910007785B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019880017051A KR910007785B1 (ko) 1988-12-20 1988-12-20 전원공급전압 변동에 대해 안정한 씨모스 입력 버퍼회로
US07/289,731 US4890051A (en) 1988-12-20 1988-12-27 CMOS input buffer stable for the variation of a power supplying voltage
JP63328076A JPH088481B2 (ja) 1988-12-20 1988-12-27 Ｃｍｏｓ入力バッファ回路
NL8903056A NL191426C (nl) 1988-12-20 1989-12-13 CMOS ingangsbuffertrap.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880017051A KR910007785B1 (ko) 1988-12-20 1988-12-20 전원공급전압 변동에 대해 안정한 씨모스 입력 버퍼회로

Publications (2)

Publication Number Publication Date
KR900011155A true KR900011155A (ko) 1990-07-11
KR910007785B1 KR910007785B1 (ko) 1991-10-02

Family

ID=19280404

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880017051A KR910007785B1 (ko) 1988-12-20 1988-12-20 전원공급전압 변동에 대해 안정한 씨모스 입력 버퍼회로

Country Status (4)

Country Link
US (1) US4890051A (ko)
JP (1) JPH088481B2 (ko)
KR (1) KR910007785B1 (ko)
NL (1) NL191426C (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3147395B2 (ja) * 1990-05-07 2001-03-19 セイコーエプソン株式会社 集積回路及び電子機器
US5019728A (en) * 1990-09-10 1991-05-28 Ncr Corporation High speed CMOS backpanel transceiver
JPH04360312A (ja) * 1991-06-06 1992-12-14 Hitachi Ltd 半導体集積回路装置と信号処理装置
JP3247402B2 (ja) * 1991-07-25 2002-01-15 株式会社東芝 半導体装置及び不揮発性半導体記憶装置
JP3122239B2 (ja) * 1992-07-23 2001-01-09 株式会社東芝 半導体集積回路
US5304872A (en) * 1992-08-10 1994-04-19 Intel Corporation TTL/CMOS input buffer operable with three volt and five volt power supplies
JP3562725B2 (ja) * 1993-12-24 2004-09-08 川崎マイクロエレクトロニクス株式会社 出力バッファ回路、および入出力バッファ回路
KR100392556B1 (ko) * 1994-01-31 2003-11-12 주식회사 하이닉스반도체 시모스회로용입력버퍼
US5554942A (en) * 1995-03-13 1996-09-10 Motorola Inc. Integrated circuit memory having a power supply independent input buffer
KR0157886B1 (ko) * 1995-07-22 1999-03-20 문정환 반도체 메모리의 입력 버퍼 회로
EP0919891B1 (de) * 1997-11-26 2004-09-29 Infineon Technologies AG Anordnung und Verfahren zur Anpassung von Ausgangstreibern von integrierten Schaltungen an die gegebenen Verhältnisse

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4453121A (en) * 1981-12-21 1984-06-05 Motorola, Inc. Reference voltage generator
JPS58207728A (ja) * 1982-05-28 1983-12-03 Nec Corp トランジスタ回路
US4472647A (en) * 1982-08-20 1984-09-18 Motorola, Inc. Circuit for interfacing with both TTL and CMOS voltage levels
US4555642A (en) * 1983-09-22 1985-11-26 Standard Microsystems Corporation Low power CMOS input buffer circuit
US4612461A (en) * 1984-02-09 1986-09-16 Motorola, Inc. High speed input buffer having substrate biasing to increase the transistor threshold voltage for level shifting
US4593212A (en) * 1984-12-28 1986-06-03 Motorola, Inc. TTL to CMOS input buffer
US4642488A (en) * 1985-09-03 1987-02-10 Codex Corporation CMOS input buffer accepting TTL level inputs
US4677321A (en) * 1985-09-10 1987-06-30 Harris Corporation TTL compatible input buffer
US4707623A (en) * 1986-07-29 1987-11-17 Rca Corporation CMOS input level shifting buffer circuit
US4763022A (en) * 1987-01-05 1988-08-09 Gte Communication Systems Corporation TTL-to-CMOS buffer

Also Published As

Publication number Publication date
JPH088481B2 (ja) 1996-01-29
NL8903056A (nl) 1990-07-16
NL191426C (nl) 1995-07-17
US4890051A (en) 1989-12-26
JPH02185116A (ja) 1990-07-19
NL191426B (nl) 1995-02-16
KR910007785B1 (ko) 1991-10-02

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E701 Decision to grant or registration of patent right
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