KR900008964Y1 - Vertical signal size adjusting circuit - Google Patents

Vertical signal size adjusting circuit Download PDF

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Publication number
KR900008964Y1
KR900008964Y1 KR2019870012542U KR870012542U KR900008964Y1 KR 900008964 Y1 KR900008964 Y1 KR 900008964Y1 KR 2019870012542 U KR2019870012542 U KR 2019870012542U KR 870012542 U KR870012542 U KR 870012542U KR 900008964 Y1 KR900008964 Y1 KR 900008964Y1
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KR
South Korea
Prior art keywords
vertical
exor
resistor
circuit
vertical size
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KR2019870012542U
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Korean (ko)
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KR890003800U (en
Inventor
이남수
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주식회사 금성사
최근선
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Priority to KR2019870012542U priority Critical patent/KR900008964Y1/en
Publication of KR890003800U publication Critical patent/KR890003800U/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
    • H04N3/223—Controlling dimensions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/37—Details of the operation on graphic patterns
    • G09G5/373—Details of the operation on graphic patterns for modifying the size of the graphic pattern

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Details Of Television Scanning (AREA)

Abstract

내용 없음.No content.

Description

수직크기 조절회로Vertical size control circuit

제 1 도는 종래의 수직크기 조절회로도.1 is a conventional vertical size control circuit diagram.

제 2 도는 본 고안의 수직크기 조절회로도.2 is a vertical size adjustment circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 수직발진회로 TR1, TR2: 트랜지스터1: vertical oscillation circuit TR 1 , TR 2 : transistor

ExOR1, ExOR2: 익스클루시브오아게이트 R1-R7: 저항ExOR 1 , ExOR 2 : Exclusive OA gate R 1- R 7 : Resistance

VR1-VR3: 가변저항 VS : 수직동기입력단자VR 1 -VR 3 : Variable resistance VS: Vertical synchronous input terminal

HS : 수평동기입력단자 C1, C2: 콘덴서HS: Horizontal synchronous input terminal C 1 , C 2 : Condenser

본 고안은 컴퓨터의 주변장치로 사용되는 모니터에 있어서, 수직크기를 조절하는 수직크기 조절회로에 관한 것으로, 특히 입력되는 수직 및 수평동기신호의 극성에 따라 수직크기를 자동으로 조절하게 한 수직크기 조절회로에 관한 것이다.The present invention relates to a vertical size adjustment circuit for adjusting the vertical size in a monitor used as a peripheral device of a computer, and in particular, the vertical size adjustment for automatically adjusting the vertical size according to the polarity of the vertical and horizontal synchronization signals inputted. It is about a circuit.

종래의 수직크기 조절회로는 제 1 도에 도시한 바와 같이 수직발진회로(1)에 저항(R1) 및 가변저항(VR1)을 직렬로 접속하여 가변저항(VR1)의 가변에 따라 수직발진회로(1)의 발진신호의 진폭이 가변되면서 수직크기가 가변되게 하였으므로 컴퓨터에서 수직크기가 각기 다른 여러 가지의 모드신호를 입력시킬 경우에는 일일이 가변저항(VR1)을 가변하여 수직크기를 조절해야 되는 결함이 있었다.In the conventional vertical size control circuit, a resistor R 1 and a variable resistor VR 1 are connected in series to the vertical oscillation circuit 1 as shown in FIG. 1 to vertically change the variable resistor VR 1 . Since the amplitude of the oscillation signal of the oscillation circuit 1 is varied so that the vertical size is varied, when the computer inputs various mode signals having different vertical sizes, the variable resistance VR 1 is adjusted to adjust the vertical size. There was a flaw to be made.

본 고안은 이와 같은 종래의 결함을 감안하여, 수직 및 수평동기신호의 극성에 따라 수직크기를 자동으로 조절하게 안출한 것으로, 이를 첨부된 제 2 도의 도면에 의하여 상세히 설명하면 다음과 같다.The present invention is conceived to automatically adjust the vertical size in accordance with the polarity of the vertical and horizontal synchronization signal in view of the conventional defects, as described in detail with reference to the accompanying drawings of FIG.

제 2 도에 도시한 바와같이 수직발진회로(1)에 저항(R1) 및 가변저항(VR1)을 직렬접속하여 수직크기를 조절하는 수직크기 조절회로에 있어서, 수직 및 수평동기입력단자(VS)(HS)를 저항(R2, R3)(R5, R6)에 접속함과 아울러 전원단자(Vcc)와 함께 익스클루시브오아게이트(ExOR1)(ExOR2)를 통하고, 저항(R4)(R7)을 통해 콘덴서(C1)(C2) 및 트랜지스터(TR1)(TR2)의 베이스에 접속하고, 트랜지스터(TR1)(TR2)의 콜렉터는 가변저항(VR2)(VR3)을 통해 상기 저항(R1) 및 가변저항(VR1)의 접속점에 접속하여 구성한 것이다.As shown in FIG. 2, in the vertical size adjusting circuit for connecting the resistor R 1 and the variable resistor VR 1 in series with the vertical oscillating circuit 1 to adjust the vertical size, the vertical and horizontal synchronous input terminals ( VS (HS) is connected to resistors R 2 and R 3 (R 5 and R 6 ), and through Exclusive Ogate (ExOR 1 ) (ExOR 2 ) with power supply terminal (Vcc), The resistors R 4 and R 7 are connected to the bases of the capacitors C 1 (C 2 ) and the transistors TR 1 (TR 2 ), and the collectors of the transistors TR 1 (TR 2 ) are variable resistors. It is configured by connecting to the connection point of the resistor R 1 and the variable resistor VR 1 through (VR 2 ) (VR 3 ).

이와 같이 구성된 본 고안의 작용효과를 상세히 설명하면 다음과 같다.Referring to the effect of the present invention configured in this way in detail as follows.

전원단자(Vcc)에 전원이 인가되고, 입력단자(VS)(HS)로 고전위의 수직 및 수평동기신호가 입력되면, 그 고전위의 수직 및 수평동기신호는 익스클루시브오아게이트 (ExOR1)(ExOR2)의 일측입력단자에 인가되고, 익스클루시브오아게이트(ExOR1)(ExOR2)의 타측입력단자에는 전원단자(Vcc)의 전원이 인가되어 있으므로 익스클루시브오아게이트(ExOR1)(ExOR2)는 모두 저전위를 출력하고, 이에 따라 트랜지스터(TR1, TR2)의 베이스에 저전위가 인가되어 그가 오프되므로 가변저항(VR2, VR3)은 접지되지 않고, 수직발진회로(1)는 저항(R1) 및 가변저항(VR1)의 값에 따라 일정진폭을 가지는 발진신호를 출력하여 수직출력회로에 입력된다.When power is applied to the power supply terminal Vcc, and the high potential vertical and horizontal synchronization signals are input to the input terminal VS HS, the high potential vertical and horizontal synchronization signals are converted into an exclusive oragate (ExOR 1). ) (is applied to one side input terminal of the ExOR 2), exclusive of Iowa gate (ExOR 1) (the other input terminal of the ExOR 2) because there is applied to the power supply of the power supply terminal (Vcc) exclusive Iowa gate (ExOR 1 (ExOR 2 ) all output low potential, and accordingly, the low potential is applied to the bases of the transistors TR 1 and TR 2 so that they are turned off, so that the variable resistors VR 2 and VR 3 are not grounded, but the vertical oscillation The circuit 1 outputs an oscillation signal having a constant amplitude according to the values of the resistor R 1 and the variable resistor VR 1 and is input to the vertical output circuit.

그리고, 입력단자(VS)(HS)로 저전위 및 고전위의 수직 및 수평동기신호가 입력되어 익스클루시브오아게이트(ExOR1)(ExOR2)의 일측입력단자에 인가되면, 익스클루시브오아게이트(ExOR1)(ExOR2)는 각기 고전위 및 저전위를 출력하여 트랜지스터(TR1)는 온되고, 트랜지스터(TR2)는 오프되므로 가변저항(VR2)이 트랜지스터(TR1)를 통해 등가적으로 접지되고, 수직발진회로(1)는 저항(R1) 및 가변저항(VR1, VR2)의 값에 따라 일정진폭의 발진신호를 출력하여 수직출력회로에 입력된다.When the low and high potential vertical and horizontal synchronous signals are input to the input terminal VS (HS) and applied to one input terminal of the exclusive ogate ExOR 1 and ExOR 2 , the exclusive oar The gates ExOR 1 and ExOR 2 output high and low potentials, respectively, so that the transistor TR 1 is on and the transistor TR 2 is off, so that the variable resistor VR 2 passes through the transistor TR 1 . Equivalently grounded, the vertical oscillation circuit 1 outputs an oscillation signal having a constant amplitude according to the values of the resistors R 1 and the variable resistors VR 1 and VR 2 and is input to the vertical output circuit.

또한, 입력단자(VS)(HS)로 고전위 및 저전위의 수직 및 수평동기신호가 입력되면, 익스클루시브오아게이트(ExOR1)(ExOR2)는 각기 저전위 및 고전위를 출력하여 트랜지스터(TR1)는 오프되고, 트랜지스터(TR2)는 온 되므로 가변저항(VR3)이 트랜지스터(TR2)를 통해 등가적으로 접지되고, 수직발진회로(1)는 저항(R1) 및 가변저항(VR1, VR3)의 값에 따라 일정진폭의 발진신호를 출력하여 수직출력회로에 입력된다.In addition, when the vertical and horizontal synchronous signals of the high potential and the low potential are input to the input terminal VS (HS), the exclusive ogate ExOR 1 and ExOR 2 output the low potential and the high potential, respectively. Since TR 1 is turned off and transistor TR 2 is turned on, variable resistor VR 3 is equivalently grounded through transistor TR 2 , and vertical oscillation circuit 1 is connected to resistor R 1 and variable. According to the values of the resistors VR 1 and VR 3 , an oscillation signal having a constant amplitude is output and input to the vertical output circuit.

이상에서 상세히 설명한 바와 같이 본 고안은 수직 및 수평동기신호의 극성에 따라 수직발진회로의 발진신호의 진폭을 가변시켜 수직크기를 자동으로 조절하므로 입력되는 신호에 따라 사용자가 수직크기를 일일이 조정해야 되는 번거로움을 제거할 수 있는 효과가 있다.As described in detail above, the present invention automatically adjusts the vertical size by varying the amplitude of the oscillation signal of the vertical oscillation circuit according to the polarity of the vertical and horizontal synchronizing signals, so that the user must manually adjust the vertical size according to the input signal. There is an effect that can eliminate the hassle.

Claims (1)

수직발진회로(1)에 저항(R1) 및 가변저항(VR1)을 직렬로 접속하여 수직크기를 조절하는 수직크기 조절회로에 있어서, 수직 및 수평동기입력단자(VS)(HS)를 전원단자(Vcc)와 함께 익스클루시브오아게이트(ExOR1)(ExOR2)를 통해 트랜지스터(TR1)(TR2)의 베이스에 접속하고, 트랜지스터(TR1)(TR2)의 콜렉터는 가변저항(VR1)(VR3)을 통해 상기 저항(R1) 및 가변저항(VR1)의 접속점에 접속하여 구성함을 특징으로 하는 수직크기 조절회로.In the vertical size adjusting circuit for connecting the resistor R 1 and the variable resistor VR 1 in series with the vertical oscillating circuit 1 to adjust the vertical size, the vertical and horizontal synchronous input terminals VS and HS are supplied with power. the collector of terminal exclusive Iowa gate (ExOR 1) (ExOR 2) via connection to the base of the transistor (TR 1) (TR 2) , and a transistor (TR 1) (TR 2) with the (Vcc) is a variable resistor (VR 1 ) (VR 3 ) vertical size control circuit, characterized in that configured to connect to the connection point of the resistor (R 1 ) and the variable resistor (VR 1 ).
KR2019870012542U 1987-07-30 1987-07-30 Vertical signal size adjusting circuit KR900008964Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019870012542U KR900008964Y1 (en) 1987-07-30 1987-07-30 Vertical signal size adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019870012542U KR900008964Y1 (en) 1987-07-30 1987-07-30 Vertical signal size adjusting circuit

Publications (2)

Publication Number Publication Date
KR890003800U KR890003800U (en) 1989-04-13
KR900008964Y1 true KR900008964Y1 (en) 1990-09-29

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Application Number Title Priority Date Filing Date
KR2019870012542U KR900008964Y1 (en) 1987-07-30 1987-07-30 Vertical signal size adjusting circuit

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KR890003800U (en) 1989-04-13

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