KR900007002Y1 - Circuit for generating scan start signal and dot clock signal - Google Patents

Abstract

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Description

Scan start signal and dot clock signal generation circuit

1 is a conventional generation circuit diagram.

2 is a generation circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

11,12: Latch 13-15,18: Counter

16: clock generator 17, 19, 20: flip-flop

I ₁ : Inverter OR ₁ : Oagate

OPC ₁ , OPC ₂ : Output port control signal DB: Data bus

CLK: Clock signal SOS: Scan start signal

: Beam detection signal DCLK: Dot clock signal

Vcc: Power Terminal

The present invention relates to a scan start signal and a dot clock signal generation circuit for generating a dot clock signal and a scan indicator signal used as a basic signal when a laser printer prints a data signal.

The conventional generation circuit has a beam detection signal as shown in FIG. Is the trigger terminal of monomulti (1) And reset terminals of the flip-flop 2 Output terminal of the mono-multi (1) Is a flip-flop (2), a clock terminal (CK ₂₎ flip-flop (2) the output terminal (Q ₂₎ to start scan signal (SOS) to the output bin with the addition that the output terminal (Q ₂₎ of the connected to the counter ( 4), reset terminal The clock signal CLK output from the clock generator 3 is applied to the clock terminal CK _{4 of} the counter 4 so that the clock signal CLK is output to the output terminal Q ₄ of the counter 4. Is configured to output a dot clock signal DCLK divided by 1/4 or 1/8.

1, reference numerals R ₁ and C ₁ in the description of the drawings denote resistors and capacitors for determining the time constant of the monomulti 1, and Vcc is a power supply terminal.

The power is applied to the conventionally generated power supply terminal Vcc configured as described above, the clock generator 3 generates the clock signal CLK and is applied to the clock terminal CK ₄ of the counter 4, and the laser printer generates data. As the printing of the signal starts, the low potential beam detection signal BD corresponding to the horizontal synchronizing signal is input from the laser printer engine to trigger the terminal of the mono multi. And reset terminals of the flip-flop 2 When is applied to, the mono multi (1) is triggered to output terminal The low potential is output, and the flip-flop 2 is reset to output the low potential to the output terminal Q ₄ , so that the counter 4 is reset to not output the dot clock signal DCLK.

In this state, high potential beam detection signal Is input to reset the flip-flop 2, and when the time constant time of the resistor R ₁ and the capacitor C ₁ elapses, the mono multi 1 output terminal. Outputs the high-potential scan start signal (SOS), and the output scan start signal (SOS) is a reset terminal of the counter (4). Since the counter 4 is reset to release the counter 4, the counter 4 counts the clock signal CLK of the clock generator 3 to output a 1/4 or 1/8 divided dot clock signal DCLK. do.

However, such a conventional generating circuit has a beam sensing signal on the half side of which the configuration is simple. A technique for synchronizing with the dot clock signal DCLK is required. That is, the beam Garage signal Is input from the laser printer engine, and the clock generator 3 cannot be reset so that the beam detection signal The counter 4 counts the clock signal CLK of the clock generator 3 while outputting the dot clock signal DCLK while resetting the counter 4 with the scan start signal SOS generated according to FIG. In this case, assuming that the dot clock signal DCLK is a signal divided by 1/8 of the clock signal CLK, the beam detection signal And an error of up to 1/8 dot occurs, and the error is the beam detection signal. This is possible when the scan start signal SOS is outputted correctly, and in fact, there is a defect that occurs until the time constant error of the monomulti 1.

The present invention is designed to generate a scan start signal and a dot clock signal that are synchronized as accurately as possible according to the beam detection signal in view of such a conventional defect, which will be described in detail with reference to the accompanying drawings of FIG. same.

2 is a generation circuit diagram of the present invention, as shown in this figure. The latches 11 and 12 for storing and outputting data signals carried on the data bus DB according to the output port control ports OPC ₁ and OPC ₂ . Output ports (OT _10- OT ₁₃ , OT _14- OT ₁₇ ) (OT _20- OT ₂₃ ) to the input ports of the counters 13, 14 and 15, and the clock terminal ( The clock signal CLK output from the clock generator 16 is applied to the CK _{13 to} CK ₁₅ through the inverter I ₁ to supply the religious terminals TC ₁₃ and TC _{14 of} the counters 13 and ₁₄ . It is connected to the control terminal CI ₁₄ (CI ₁₅ ) of the counter 14, 15, and the end terminal TC ₁₅ of the counter 15 is a flip with an input terminal D ₁₇ connected to a power supply terminal Vcc. It is connected to the clock terminal CK ₁₇ of the flop 17 to output the scan start signal SOS to its output terminal Q ₁₇ , and the output signal Q ₁₇ is outputted to the clock signal. Terminal of counter 18 for counting And a dot clock signal DCLK to the output terminal Q _{18 thereof} , while the beam detection signal Is applied to the input terminal D ₁₉ of the flip-flop ₁₉ to connect its output terminal Q ₁₉ to the input terminal D ₂₀ of the flip-flop 20, and the connection point thereof is flip-flop 20. Output terminal of The rod terminal of the counter (13-15) through the ora gate (OR ₁ ) together with And reset terminal of flip-flop 17 The clock signal CLK is applied to the clock terminals CK ₁₉ and CK ₂₀ of the flip-flop 19 and 20.

According to the present invention, the power is supplied to the power supply terminal Vcc, the clock generator 16 outputs the clock signal CLK, and the data bus DB is output together with the output port control signals OPC ₁ and OPC ₂ . When a data signal is inputted to the latches 11 and 12, the latches 11 and 12 store the data signal and output ports (OT ₁₀ -OT ₁₃ , OT ₁₄ -OT ₁₇ ) (OT ₂₀ -OT _23). ) Is applied to the counters 13, 14 and 15.

In this state, high potential beam detection signal Is input to the input terminal D _{91 of the} flip-flop 19, the flip-flop 19 outputs a high potential to the output terminal (Q ₁₉ ) in accordance with the clock signal (CLK) of the flip-flop 20 The high potential is applied to the input terminal D ₂₀ and the load terminal of the counter 13-15 through the oragate OR ₁ . Since the counters 13, 14 and 15 do not load the output data signals of the latches 11 and 12, the flip-flop 20 outputs the output terminal according to the clock signal CLK. Will output low potential.

In this state, the low potential beam detection signal Is input, the flip-flop 19 outputs a low potential to the output terminal Q ₁₉ in synchronization with the clock signal CLK, and the flip-flop 20 outputs the output terminal as described above. The low potential is output, so the ogaate (OR ₁ ) is a low potential load signal ( ) And load terminal of counter (13-15) And reset terminal of flip-flop 17 The counters 13, 14 and 15 thus load data signals output from the latches 11 and 12, and the flip-flop 17 is reset to lower the potential to the output terminal Q ₁₇ . The counter 18 is reset, and the counter 18 is reset.

When the clock signal CLK is inverted through the inverter I ₁ and applied to the clock terminals CK _{13 to} CK ₁₅ of the counter 13-15, the clock signal CLK is counted from the value of the loaded data signal of the counter 13. When the counting of the counter 13 ends, the high potential is output to the end terminal TC ₁₃ and applied to the control terminal I _{14 of the} counter 14, so that the value of the data signal loaded by the counter 14 is increased. Starts counting, and when the count of the counter 14 ends, the high potential is output to the end terminal TC ₁₃ and applied to the control terminal CI _{14 of the} counter 14 so that the counter 14 is loaded. Counting starts from the value of the signal, and when the counting of the counter 14 ends, the counter ₁₅ is output to the control terminal CI ₁₅ of the counter 14 by outputting a high potential to the ending terminal TC ₁₄ . Counting starts from the value of the stored data signal.

When the count of the counter 13-15 ends in this way, and the high potential is output to the end terminal TC ₁₄ of the counter 15, the output high potential is transmitted to the clock terminal 9CK ₁₇ of the flip-flop ₁₇ . Since it is applied as a clock signal, the flip-flop 17 outputs the high-potential scan start signal SOS to the output terminal Q ₁₇ , and the output scan start signal SOS is the reset terminal of the counter 180. Since the counter 18 is released when the counter 18 is reset, the counter 18 counters the clock signal CLK to output the dot clock signal DCLK.

Since the counter 13-15 can count up to 12 bits, the beam detection signal is output when the clock signal CLK is divided into 1 / 8ths and the dot clock signal DCLK is output. After inputting, the maximum time of 512 dot clocks can be adjusted until the scan start signal SOS is output.

As described in detail above, the present invention has an error of only 1 / n dot clock signal when using an n-times dot clock signal, and the time until the scan start signal is output after the beam detection signal is input. It can be easily adjusted to print on various papers.

Claims (1)

Output ports (OT _10- OT ₁₃ , OT _14- OT _{17 of} latches 11 and 12 for storing and outputting data signals according to the data bus DB in accordance with the output port control signals OPC ₁ and OPC ₂ . (OT ₂₀ -OT ₂₃ ) is connected to the input ports of the counters 13, 14 and 15, and the clock terminals CK _{13 to} CK ₁₅ of the counters 13-15 are output from the clock generator 16. The clock signal CLK is applied through the inverter I ₁ so that the religious terminals TC ₁₃ and TC ₁₄ of the counters ₁₃ and _{14 are} transferred to the control terminals CI ₁₄ of the counters 14 and 15 ( CI ₁₅ ), and the termination terminal TC ₁₅ of the counter 15 is connected to the clock terminal CK ₁₇ of the flip-flop ₁₇ whose input terminal D _{17 is} connected to the power supply terminal Vcc. The scan start signal SOS is output to the output terminal Q ₁₇ and the output signal Q ₁₇ is output to the clock signal. Terminal of counter 18 for counting And a dot clock signal DCLK to the output terminal Q _{18 thereof} , while the beam detection signal Is applied to the input terminal D ₁₉ of the flip-flop ₁₉ to connect its output terminal Q ₁₉ to the input terminal D ₂₀ of the flip-flop 20, and the connection point thereof is flip-flop 20. Output terminal of The rod terminal of the counter (13-15) through the ora gate (OR ₁ ) together with And reset terminal of flip-flop 17 And a clock start signal (CLK) is applied to the clock terminals (CK ₁₉ ) (CK ₂₀ ) of the flip-flop (19) (20).