KR900001984B1 - Rasin sealing type semiconductor device - Google Patents

Rasin sealing type semiconductor device Download PDF

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KR900001984B1
KR900001984B1 KR1019860006424A KR860006424A KR900001984B1 KR 900001984 B1 KR900001984 B1 KR 900001984B1 KR 1019860006424 A KR1019860006424 A KR 1019860006424A KR 860006424 A KR860006424 A KR 860006424A KR 900001984 B1 KR900001984 B1 KR 900001984B1
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South Korea
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resin
heat sink
semiconductor device
mold layer
bed
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KR1019860006424A
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Korean (ko)
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KR870009453A (en
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도시히로 가토
신지로 고지마
다카오 에모토
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가부시끼가이샤 도오시바
와타리 스기이찌로
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Abstract

내용 없음.No content.

Description

수지봉합형 반도체장치Resin Sealed Semiconductor Device

제1도는 본 발명의 일실시예에 따른 수지봉합형 반도체장치의 단면도.1 is a cross-sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention.

제2도는 제1도중 히트싱크의 일례를 나타내는 평면도.2 is a plan view showing an example of the heat sink in FIG.

제3도는 제1도중 리이드프레임의 일례를 나타내는 평면도.3 is a plan view showing an example of the lead frame in FIG.

제4a도 내지 제4e도는 제1도중 베드부의 배면과 히트싱크의 상면에 형성시킨 오목부의 서로 다른 예를 나타내는 평면도.4A to 4E are plan views showing different examples of recesses formed on the rear surface of the bed portion and the upper surface of the heat sink in FIG.

제5도는 제1도에 도시된 수지봉합형 반도체장치의 외관을 나타내는 정면도.FIG. 5 is a front view showing the appearance of the resin-sealed semiconductor device shown in FIG.

제6도는 제1도에 도시된 수지봉합형 반도체장치의 적용례인 파워트랜지스터어레이의 일례를 나타내는 회로도이다.FIG. 6 is a circuit diagram showing an example of a power transistor array which is an application example of the resin-sealed semiconductor device shown in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 히트싱크 2 : 리이드프레임1: Heat sink 2: Lead frame

3 : 마운트층 4 : 반도체칩3: mount layer 4: semiconductor chip

5 : 접합선 6 : 수지모울드층5: junction line 6: resin mold layer

61: 제1수지모울드층 62: 제2수지모울드층6 1 : 1st resin mold layer 6 2 : 2nd resin mold layer

7, 8 : 오목부 11 : 피스고정홈7, 8: recess 11: peace piece groove

21 : 베드부 22 : 리이드패턴부21: bed portion 22: lead pattern portion

23 : 프레임부23: frame portion

본 발명은 수지봉합형 반도체장치에 관한 것으로, 특히 반도체칩에 대해 절연된 히트싱크를 갖춘 수지봉합형 반도체 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device having a heat sink insulated from a semiconductor chip.

일반적으로 파워트랜지스터어레이와 같은 전력용 반도체장치에서는 1개의 히트싱크상에다 복수개의 반도체칩을 설치하여 조립한 다음 이를 하나의 수지모울드층으로 봉합한 형태의 반도체장치가 사용되고 있는데, 이와같은 반도체장치에서는 필히 개개의 반도체칩과 히트싱크간을 절연시키지 않으면 않되므로 처음에는 세라믹기판을 사용하였으나, 이는 비용이 고가이고 가공에 문제점을 안고 있다는 점에서 종종 다른 대체안이 제안되고 있다.In general, in a power semiconductor device such as a power transistor array, a semiconductor device in which a plurality of semiconductor chips are installed on one heat sink and assembled and then sealed with a resin mold layer is used. Since the individual semiconductor chip and the heat sink must be insulated, ceramic substrates were used at first. However, other alternatives are often proposed in that they are expensive and have problems in processing.

본 발명자도 세라믹기판을 사용하지 않고 통상의 금속제 히트싱크만을 사용하여 각각의 반도체칩간을 절연시킨 수지봉합형 반도체장치의 구조에 대하여 안을 낸바 있으며, 또한 그에 대한 개량방안에 대해 1985년 일본특허출원 134,658호에서 제안한 바 있는데, 위에서 언급한 보다 개량된 수지봉합형 반도체장치는 금속으로 된 베드부의 표면에 설치된 반도체칩과, 상기 베드부에 배면이 노출되도록 상기 베드부와 상기 반도체칩을 봉합한 제1수지모울드층, 상기 베드부의 노출된 배면 아래에서 소정의 거리를 두고 배치된 금속제 히트싱크와 상기 제1수지모울드층의 외주측면을 피복시키고, 또 상기 베드부의 배면과 상기 히트싱크간의 간극에 채워서 형성시킨 제2수지모울드층, 상기 제2수지모울드층을 관통하여 그 선단부를 상기 제1수지모울드층내에 배치시킴과 더불어 접합선을 통해 상기 반도체칩표면의 내부단자에 접속시킨 리이드를 구비한 것을 특징으로 하는 것인데, 이러한 구조로 된 반도체장치는 수지모울드층을 2층으로 나눈 것을 기술적 요지로 하는 것이므로 제1수지모울드층을 형성시킨다음 트랜스퍼모울드하여 제2수지모울드층을 제조하게 된다. 이러한 경우 1단계만의 트랜스퍼모울드에 의한 종래의 경우와는 용융수지의 유형이 다르고, 최종적으로 기포가 발생되기 쉬운 부분은 베드부분과 히트싱크와의 간극에서가 아니라 제1수지모울드층의 외측부분에 발생되기 쉽다. 그 결과 제2수지모울드층으로서 점도높은 수지를 사용하고, 또 베드부와 히트싱크간의 간극을 좁게한 경우에도 그 간극속에 채워넣게 되는 수지층에 기포가 형성되는 것을 방지할 수가 있다. 따라서, 제2수지모울드층으로서 실리카의 함유량이 높은 고열전도율의 수지를 사용하여 절연성을 유지하면서 방열특성을 향상시킬 수 있다.The present inventor has also devised a structure of a resin-sealed semiconductor device which insulates each semiconductor chip by using only a normal metal heat sink without using a ceramic substrate, and further, a method for improvement thereof is disclosed in Japanese Patent Application No. 134,658 in 1985. As proposed above, the above-mentioned improved resin-sealed semiconductor device includes a semiconductor chip provided on a surface of a metal bed portion, and a first sealing portion of the bed portion and the semiconductor chip to expose the rear surface of the bed portion. A resin mold layer and a metal heat sink disposed at a predetermined distance below the exposed back surface of the bed portion and the outer circumferential side surface of the first resin mold layer are coated to fill a gap between the back surface of the bed portion and the heat sink. The tip of the second resin mold layer and the second resin mold layer, and the tip of the second resin mold layer is formed in the first resin mold layer. And a lead connected to the internal terminal of the surface of the semiconductor chip through a bonding line. The semiconductor device having such a structure is a technical gist of the resin mold layer divided into two layers. After the resin mold layer is formed, the second resin mold layer is manufactured by transfer molding. In this case, the type of molten resin is different from the conventional case by the transfer mold of only one step, and the part which is likely to generate bubbles finally is not at the gap between the bed part and the heat sink, but at the outer part of the first resin mold layer. Easy to occur in. As a result, even when the resin having high viscosity is used as the second resin mold layer and the gap between the bed portion and the heat sink is narrowed, bubbles can be prevented from being formed in the resin layer to be filled in the gap. Therefore, the heat dissipation characteristic can be improved, maintaining insulation, using resin of high thermal conductivity with high silica content as a 2nd resin mold layer.

또 제2수지모울드층을 형성시킬때에는 이미 제1수지모울드층이 형성되어 있으므로 점성이 높은 용융수지에 의한 트랜스퍼모울드에 있어서도 접합불량등의 문제는 발생되지 않는다.When the second resin mold layer is formed, the first resin mold layer is already formed, so that problems such as poor bonding are not caused even in the transfer mold by the highly viscous molten resin.

그러나, 이와 같은 구조로 반도체장치를 시험제작하여 방열특성을 측정해본 바로는 반드시 충분한 특성이 얻어지지 않고 더구나 그 분산이 크다고 하는 문제가 있었기에 그 원인을 찾아본 결과 베드의 배면과 제2수지모울드층의 경계면 사이에 약간의(수 미크론정도) 기포층이 형성되어 있다는 것을 알았다. 이는 반도체장치의 제조시 사용한 트랜스퍼모울드수지와 금속제 베드와의 접착력이 충분치 못함에 기인한 것이며 상기 기포층이 존재하게 되므로 말미암아 열전도성이 충분하여 얻어지지 않는다는 것을 알았다.However, as a result of the test fabrication of semiconductor devices with such a structure, the heat dissipation characteristics were not necessarily obtained, and there was a problem that the dispersion was large. As a result, the back of the bed and the second resin mold layer were found. It was found that a slight (a few microns) bubble layer was formed between the interfaces of the. This was due to the insufficient adhesion between the transfer mold resin and the metal bed used in the manufacture of the semiconductor device, and it was found that thermal conductivity was not obtained due to the existence of the bubble layer.

본 발명은 상기한 바와 같은 금속제 베드부의 배면과 수지모울드층간에 충분한 열전도가 이루어지지 않는다고 하는 문제점을 개선하기 위한 것으로, 상기 열전도특성과 반도체장치의 방열특성을 대폭 개선시킬 수 있음과 더불어 상기 베드부의 기계적 강도가 높은 수지봉합형 반도체장치를 제공하고자 함에 발명의 목적이 있다.The present invention is to solve the problem that the sufficient thermal conductivity is not made between the back surface of the metal bed portion and the resin mold layer as described above, it is possible to significantly improve the thermal conductivity and heat dissipation characteristics of the semiconductor device and the bed portion An object of the present invention is to provide a resin-sealed semiconductor device having high mechanical strength.

본 발명은 금속으로 된 베드부위에 반도체칩을 설치하고, 그 표면의 내부단자를 접합선에 의해 리이드의 선단부에 접속시키며, 이것을 상기 베드부에 배면이 노출되도록 제1수지모울드층으로 봉합한 다음, 상기 베드부의 배면아래에 소정 간격을 두고 금속으로 된 히트싱크가 위치하도록 배치하여 상기 간격부에 채워넣음과 더불어, 상기 제1수지모울드층의 측면과 히트싱크의 측면 및 상기 리이드의 중간부를 피복시키도록 제2수지모울드층을 형성시켜서된 수지봉합형 반도체장치에 있어서, 상기 베드부의 배면에 오목부를 형성시켜서 된 것을 특징으로 하는 것이다.According to the present invention, a semiconductor chip is provided on a metal bed, and the inner terminal of the surface thereof is connected to the front end of the lead by a joining line, which is sealed with a first resin mold layer to expose the back surface of the bed. A metal heat sink is disposed under the rear surface of the bed portion at predetermined intervals to fill the gap portion, and the side surface of the first resin mold layer, the side surface of the heat sink, and the middle portion of the lead are covered. The resin-sealed semiconductor device in which a second resin mold layer is formed so as to form a recessed portion on the back surface of the bed portion.

상기한 바와 같은 2층모울드구조를 형성시키는 경우 베드부와 히트싱크간의 간격을 좁게함과 더불어, 제2수지모울드층으로서 실리카의 함유량이 높고 고열전도율을 갖는 것을 사용한 경우에도 상기 간격부에 기포가 형성되는 것을 방지할 수 있고, 절연성을 유지하면서 방열특성을 향상시킬 수 있게 된다.In the case of forming the two-layer mold structure as described above, the gap between the bed portion and the heat sink is narrowed, and even when the second resin mold layer has a high silica content and a high thermal conductivity, bubbles are formed in the gap portion. Formation can be prevented and heat dissipation characteristics can be improved while maintaining insulation.

이와같이 베드부의 배면은 오목부가 마련되어져 있으므로 제2수지모울드층과 접촉면적이 크게 되고, 베드부의 제2수지모울드층간의 열전도성이 향상됨에 따라 베드부와 히트싱크간의 열저항이 작아지게 되므로써 방열특성이 크게 개선되어지는 것이다.Thus, the back surface of the bed portion is provided with a concave portion, so that the contact area with the second resin mold layer is increased, and as the thermal conductivity between the second resin mold layer of the bed portion is improved, the thermal resistance between the bed portion and the heat sink is reduced, which results in heat dissipation. This is a great improvement.

이하, 도면에 의거 본 발명의 일실시예에 대해 상세히 설명하면 다음과 같다. 제1도에 있어서 참조부호 1은 알루미늄판 또는 구리판등과 같은 열전도성이 높은 금속판으로 제작된 히트싱크로서 그 평면구조는 예를 들어 제2도에 도시된 바와같은 것으로 방열판(도시하지 않음)에 고정시키기 위한 피스고정홈(11)이 형성된 것이고, 21은 리이드프레임(2)의 베드부로서 구리계열이나 철계열등의 도전성금속판이 예컨대 제3도에 도시된 바와같이 패터닝되어 형성된 것이다. 상기 리이드프레임(2)에는 독립된 4개의 베드부(21)와 리이드패턴부(22)가 형성되어 프레임부(23)에 연결되어 지지된 것이다. 상기 베드부(21)는 그 크기가 예컨대 10mm×10mm이고, 그 위에는 납합금등으로 된 마운트층(3)에 의해 반도체칩(4)이 다이본딩된 것이며, 상기 반도체칩(4)의 표면상에 있는 내부단자는 구리, 알루미늄등의 가는 금속선으로 이루어진 접합선(5)에 의해 상기 리이드패턴부(22)의 선단부간에 필요한 전기적 접속이 이루어진 것이다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, reference numeral 1 denotes a heat sink made of a high thermal conductive metal plate such as an aluminum plate or a copper plate, and the planar structure thereof is as shown in FIG. 2, for example, to a heat sink (not shown). A piece fixing groove 11 for fixing is formed, and 21 is a bed portion of the lead frame 2 formed by patterning a conductive metal plate such as copper series or iron series, for example, as shown in FIG. In the lead frame 2, four independent bed portions 21 and lead pattern portions 22 are formed and connected to and supported by the frame portion 23. The bed portion 21 has a size of, for example, 10 mm x 10 mm, on which the semiconductor chip 4 is die-bonded by a mount layer 3 made of a lead alloy or the like, on the surface of the semiconductor chip 4. The internal terminal in is made of the electrical connection necessary between the leading end of the lead pattern portion 22 by a bonding line 5 made of thin metal wire such as copper, aluminum.

상기한 베드부(21)의 리이드패턴부(22)의 선단부, 마운트층(3), 반도체칩(4) 및 접합선(5)은 상기 베드부(21)의 배면이 노출되도록 제1수지모울드층(61)에 의해 모울드되어 있고, 상기 베드부(21)의 배면하측에 소정거리(예를들어 0.3mm)를 두고 상기 히트싱크(1)가 배치되어 있으며, 이러한 것들간의 간극을 채워넣음과 더불어 상기 제1수지모울드층(61)의 측면과 히트싱크(1)의 측면 및 상기 히이드패턴부(22)의 중간부를 덮도록 제2수지모울드층(62)이 형성되어 있다. 즉 수지모울드층(6)이 2층구조로 되어 있고, 각 수지모울드층(61)(62)도 결정성 실리카를 함유하는 높은 열전도성 에폭시수지로 되어 있다. 이러한 경우 제1수지모울드층(61)에는λ(열전도율)=60×10-4cal/cm·sec·k의 것이 사용되고, 제2수지모울드층(62)에는 열전도율이 한층 더 높은 λ=80∼90×10-4cal/cm·sec·k의 것이 사용되고 있다.The first resin mold layer of the front end portion of the lead pattern portion 22, the mount layer 3, the semiconductor chip 4, and the bonding line 5 of the bed portion 21 is exposed to expose the rear surface of the bed portion 21. (6 1 ), the heat sink 1 is arranged at a predetermined distance (for example, 0.3 mm) under the rear surface of the bed portion 21, and fills the gap between them. In addition, the second resin mold layer 6 2 is formed to cover the side surface of the first resin mold layer 6 1 , the side surface of the heat sink 1, and the middle portion of the hide pattern portion 22. That is, the resin mold layer 6 has a two-layer structure, and each resin mold layer 6 1 , 6 2 is also made of a high thermal conductive epoxy resin containing crystalline silica. In this case the first resin molded layer (61) it is λ (thermal conductivity) = 60 × 10 -4 cal / cm · sec · is used for k, the second resin molded layer (62) has further high thermal conductivity λ = 80-90x10 <-4> cal / cm * sec * k is used.

그리고 상기 베드부(21)의 배면에는 복수개의 오목부(7)가 흩어져 형성되어 있고, 상기 히트싱크(1)의 상면에도 오목부(8)가 흩어져 형성되어 있다. 이러한 오목부(7)(8)들은 베드부의 배면과 히트싱크의 상면을 기계적으로 가공하여 미리 형성시켜 놓은 것으로, 예컨대 압인가공에 의해 다수의 오목부를 형성시킨 다음 호닝가공에 의해 면을 거칠게 한 것이다. 여기서 압인가공에 의해 형성시킨 다수의 오목부의 각종 평면형상에 대한 예가 제4도(a) 내지 (e)에 도시되어 있으며, 제4도중 (a)는 원형홈, (b)는 긴 직사각형도랑, (c)는 행렬형태로 배열된 사각홈, (d)는 바둑무늬 모양으로 배열된 사각홈, (e)는 삼각홈이다.A plurality of recesses 7 are scattered on the rear surface of the bed 21, and recesses 8 are also scattered on the upper surface of the heat sink 1. The recesses 7 and 8 are formed by mechanically machining the rear surface of the bed and the upper surface of the heat sink in advance, for example, by forming a plurality of recesses by pressing, and then roughening the surface by honing. . Here, examples of various planar shapes of the concave portions formed by the pressing process are shown in FIGS. 4A to 4E, in FIG. 4, (a) is a circular groove, (b) is a long rectangular groove, (c) is a square groove arranged in a matrix form, (d) a square groove arranged in a checkered shape, (e) is a triangular groove.

또 상기한 실시예의 수지봉합형 반도체장치를 제조할 때에는 종래와 같은 형태로 리이드프레임(2)위에서 반도체칩(4)의 다이본딩과 와이어본딩을 행한다음 트랜스퍼모울드에 의해 제1수지모울드층(61)을 형성시켜 수지봉합을 한다. 이어 트랜스퍼모울드금형내에다 히트싱크(1)를 설치하고, 수지봉합된 상기 라이드프레임(2)을 상기 히트싱크(1)의 윗쪽에 소정간극을 두고 배치 및 설치하며, 그 상태에서 트랜스퍼모울드를 하여 제2수지모울드층(62)을 형성시킨다. 상기 2번째의 트랜스퍼모울드에 있어 수지액은 먼저 히트싱크(1)와 제1수지모울드층(R1) 사이를 흐르게 되므로 제1수지모울드층(61)의 외측에서 흘러들어오게 된다. 따라서 이러한 경우 공기가 빠져나가는 곳은 제2수지모울드층(62)의 형성공간이 되어 히트싱크(1)와 제1수지모울드층(61)간의 간극부분에는 어떠한 기포도 발생되지 않게 되므로 열전도율이 높은 수지를 채워넣을 수가 있게 된다. 이와 같이 수지봉합한 다음에 리이드포밍을 하여 제작된 제품에 대한 정면외관이 제5도에 도시되어 있는데, 이 도면중 A-A'선에 따른 단면구조는 제1도에 도시되어 있다.Further, when manufacturing the resin-sealed semiconductor device of the above-described embodiment, die bonding and wire bonding of the semiconductor chip 4 are performed on the lead frame 2 in the same manner as in the prior art, and then the first resin mold layer 6 is formed by a transfer mold. 1 ) form resin sealant. Then, the heat sink 1 is installed in the transfer mold mold, and the resin-sealed ride frame 2 is disposed and installed with a predetermined gap above the heat sink 1, and then the transfer mold is formed. The second resin mold layer 6 2 is formed. In the second transfer mold, the resin liquid first flows between the heat sink 1 and the first resin mold layer R 1 , so that the resin liquid flows out of the first resin mold layer 6 1 . Therefore, in this case, the place where air escapes becomes a space for forming the second resin mold layer 6 2 , and thus no bubbles are generated in the gap portion between the heat sink 1 and the first resin mold layer 6 1 , so that the thermal conductivity is high. This high resin can be filled. The front appearance of the product fabricated by resin sealing and then lead forming is shown in FIG. 5, in which the cross-sectional structure along the line A-A 'is shown in FIG.

상기 실시예의 수지봉합형 반도체장치에 의하면, 베드부(21)는 그 배면에 다수의 오목부(7)가 형성되어 있으므로 제2수지모울드층(62)과의 접촉면적이 커지게 되어 상기 베드부(21)와 제2수지모울드층(62)간의 열전도성이 향상된다. 이와 마찬가지로 히트싱크(1)에서도 그 상면에 다수의 오목부(8)가 형성되어 있어서 제2수지모울드층(62)과의 접촉면적이 커지게 되므로 상기 제2수지모울드층(62)과 히트싱크(1)간의 열전도성이 향상된다. 따라서 베드부(21)와 히트싱크(1)간의 열저항 Rth은 종래에 제안되어졌던 것(오목부(7)(8)가 형성되지 않은 것)에 비해 대폭 감소되므로 반도체장치의 방열특성이 크게 개선되어졌고, 또 베드부(21)는 그 배면에 복수개의 오목부(7)가 형성됨에 따라 기계적 강도가 높아지게 되었다. 이와 더불어 상기 실시예의 반도체장치는 종래에 제안되어졌던 반도체장치의 구조에 비해 상기 오목부(7)(8)가 형성되어 있다는 점만이 다를 뿐이며 상기 종래의 반도체 장치가 가졌던 특징과 장점을 모두 갖춘 것이다.According to the resin-sealed semiconductor device of the above embodiment, the bed portion 21 has a plurality of recesses 7 formed on the rear surface thereof, so that the contact area with the second resin mold layer 6 2 becomes large so that the bed The thermal conductivity between the portion 21 and the second resin mold layer 6 2 is improved. Similarly, the heat sink (1) in a plurality of recesses 8 in is formed in the second resin, because the contact area becomes large with the molded layer (62) and the second resin molded layer (62) and on the upper surface The thermal conductivity between the heat sinks 1 is improved. Therefore, the thermal resistance Rth between the bed portion 21 and the heat sink 1 is greatly reduced as compared with the conventionally proposed ones (the recesses 7 and 8 are not formed). In addition, the bed portion 21 has a high mechanical strength as a plurality of recesses 7 are formed on the rear surface thereof. In addition, the semiconductor device of the embodiment differs only in that the concave portions 7 and 8 are formed in comparison with the structure of the semiconductor device that has been proposed in the related art, and has all the features and advantages of the conventional semiconductor device. .

또 본 발명은 상시 실시예에만 한정되지 않고, 오목부(7)(8)가 각각 압인가공으로만 또는 호닝가공으로만(드라이호닝이나 웨트호닝으로도 좋음) 형성된 경우에서도, 히트싱크상면에는 오목부(8)가 형성되지 않고 베드부의 배면에만 오목부(7)가 형성된 경우에서도 상기 실시예와는 동질의 효과가 얻어진다. 이러한 갖가지 경우에 대한 베드부와 히트싱크간의 열저항 Rth의 실제 측정데이터를 아래의 표에 나타내었다. 여기서 ㈀은 종래의 구조에 대한 것으로, 그 열저항 Rth가 예컨대 2.7K/W이고, ㈁∼㈄ 은 오목부의 형성장소와 형성방법의 조합이 다른 것으로, 그외의 조건은 상기 ㈀의 구조를 갖는 것의 조건과 동일한 것이다. 아래의 표에서 ㈄의 구조의 것(상기의 실시예에 해당함)에 대한 열저항 Rth는 1.6K/W로서 ㈀의 구조를 갖는 것에 비해 대략 0.6배정도 작게 되어 방열특성이 약 40%정도 개선되는 것을 알 수 있다.In addition, the present invention is not limited to the embodiment only, and concave in the heat sink upper surface even when the recesses 7 and 8 are formed only by pressing or honing, respectively (also good as dry honing or wet honing). The same effect as in the above embodiment can be obtained even when the recessed portion 7 is formed only on the rear surface of the bed portion without forming the portion 8. The actual measurement data of the thermal resistance Rth between the bed portion and the heat sink for these various cases is shown in the table below. Where k is for the conventional structure, the thermal resistance Rth is 2.7 K / W, for example, and k is the combination of the formation place and the forming method of the recess, and other conditions are different from those of Same condition. In the table below, the heat resistance Rth of the structure of fin (corresponding to the above embodiment) is 1.6K / W, which is about 0.6 times smaller than that of the fin structure, and the heat dissipation characteristics are improved by about 40%. Able to know.

Figure kpo00001
Figure kpo00001

또 상기 ㈄의 실시예에 있어, 제2수지모울드층(62)으로서 열전도율이 약간 높은 것(예를 들어 λ=85×10-4cal/cm·sec·k)을 사용하므로써 열저항 Rth을 1.40K/W이하로 할 수 있다는 것이 확인되었다.In the above embodiment, the heat resistance Rth is reduced by using a slightly high thermal conductivity (for example, λ = 85 × 10 −4 cal / cm · sec · k) as the second resin mold layer 6 2 . It was confirmed that it can be less than 1.40K / W.

제6도는 파워트랜지스터어레이의 일례로서 달링톤접속된 파워트랜지스터(60)가 6개 설치된 회로를 나타내는 것으로, 이와 같은 파워트랜지스터어레이에다 본 발명을 적용하면 그 방열특성이 좋게 되므로 다른 조건(패키지의 크기등)이 동일한 그대로 고출력화를 실현시킬 수 있었다.6 shows a circuit in which six Darlington-connected power transistors 60 are provided as an example of a power transistor array. When the present invention is applied to such a power transistor array, the heat dissipation characteristics are improved, and thus, the condition of the package is different. And the like can achieve high output.

또 본 발명은 파워트랜지스터어레이에만 한정되지 않고 다이오드어레이, 파워솔리드스레이트릴레이, 파워포토커플러등에 적용시켜도 효과적이고, 복수개의 반도체칩을 단일 패키지내에 봉합한 경우뿐만 아니라 1개의 반도체칩을 봉합한 반도체장치(파워트랜지스터등)에 적용시켜도 효과적이다.In addition, the present invention is not only limited to a power transistor array, but also effective when applied to a diode array, a power solid slate relay, a power photocoupler, and the like. It is also effective when applied to (power transistor, etc.).

상기한 바와같이 본 발명은 베드부와 히트싱크사이에다 외장용의 수지를 채워넣어 양측을 절연시킨 수지봉합형 반도체장치에 있어서, 베드부와 히트싱크간의 거리를 단축시킴과 더불어 기포의 발생을 방지할 수 있고, 또 상기 베드부와 히트싱크간에 채워넣는 수지모울드층의 결정 실리카의 함유량을 증가시켜 절연성을 유지시키면서 방열특성을 향상시킬 수 있게 된다. 그리고 상기 베드부의 배면에 오목부를 형성시켜주므로써 히트싱크와의 사이에 채워진 수지층과의 접촉면적이 커지게 되고 이에 따라 베드부와 히트싱크간의 열전도율이 좋아지게 되어 방열특성이 더욱 개선되는 장점이 있다.As described above, the present invention provides a resin-sealed semiconductor device insulated from both sides by filling an external resin between a bed portion and a heat sink, and shortens the distance between the bed portion and the heat sink and prevents the occurrence of bubbles. In addition, it is possible to increase the content of the crystalline silica of the resin mold layer to be filled between the bed portion and the heat sink to improve the heat dissipation characteristics while maintaining insulation. In addition, by forming a recess in the back of the bed, the contact area between the resin layer filled between the heat sink is increased, and thus, the thermal conductivity between the bed and the heat sink is improved, thereby further improving heat dissipation characteristics. have.

Claims (4)

베드부(21)와 상기 베드부(21)의 표면위에 설치된 반도체칩(4), 상기 반도체칩(4)의 내부단자에 접합선(5)을 통해 접속된 리이드프레임(2), 상기 베드부(21)의 배면하측에 소정거리의 간극을 두고 설치된 금속제 히트싱크(1), 상기 반도체칩(4)과 베드부(21), 접합선(5), 리이드프레임(2)선단부 및 히트싱크(1)를 봉합하는 수지모울드층(6)이 설치된 수지봉합형 반도체장치에 있어서, 상기 베드부(21)는 그 배면에 오목부(7)가 형성되고, 상기 수지모울드층(6)이 상기 베드부(21)의 배면이 노출되도록 봉합하는 제1수지모울드층(61)과 상기 히트싱크(1)의 측면과 상기 제1수지모울드층(61)의 측면 및 상기 리이드프레임(2)의 중간부를 피복함과 더불어 상기 베드부(21)의 배면과 히트싱크(1)의 상면간의 간극에 채워져 형성된 제2수지모울드층(62)으로 형성된 것을 특징으로 하는 수지봉합형 반도체장치.The bed part 21, the semiconductor chip 4 provided on the surface of the bed part 21, a lead frame 2 connected to the inner terminal of the semiconductor chip 4 through a bonding line 5, and the bed part ( A metal heat sink 1 provided with a gap of a predetermined distance below the rear surface of the back 21, the semiconductor chip 4 and the bed portion 21, the junction line 5, the leading end of the lead frame 2 and the heat sink 1 In the resin-sealed semiconductor device provided with a resin mold layer 6 for sealing the resin, the bed portion 21 has a recessed portion 7 formed on its back surface, and the resin mold layer 6 has the bed portion ( The first resin mold layer 6 1 , the side surfaces of the heat sink 1, the side surfaces of the first resin mold layer 6 1 , and the middle part of the lead frame 2 are sealed to expose the rear surface of the substrate 21. in addition to that also the coating formed of the second resin molded layer (62) filled in the gap formed between the upper surface of the back surface and the heat sink (1) of the bed portion 21 features coming A resin sealing type semiconductor device. 제1항에 있어서, 상기 히트싱크는 그 상면에 오목부(8)가 형성되어진 것을 특징으로 하는 수지봉합형 반도체장치.2. The resin-sealed semiconductor device according to claim 1, wherein a recess (8) is formed on an upper surface of the heat sink. 제1항 또는 제2항에 있어서, 상기 오목부(7)(8)는 복수개가 산재하여 형성되어진 것을 특징으로 하는 수지봉합형 반도체장치.The resin-sealed semiconductor device according to claim 1 or 2, wherein a plurality of said recesses (7) are formed interspersed. 제3항에 있어서, 상기 오목부(7)(8)는 압인가공이나 호닝가공에 의해 형성되어진 것을 특징으로 하는 수지봉합형 반도체장치.4. The resin-sealed semiconductor device according to claim 3, wherein the recesses (7) (8) are formed by pressing or honing.
KR1019860006424A 1986-03-31 1986-08-04 Rasin sealing type semiconductor device KR900001984B1 (en)

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JP61-71134 1986-03-31
JP71134 1986-03-31
JP61071134A JPH0680748B2 (en) 1986-03-31 1986-03-31 Resin-sealed semiconductor device

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KR870009453A KR870009453A (en) 1987-10-26
KR900001984B1 true KR900001984B1 (en) 1990-03-30

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US5172213A (en) * 1991-05-23 1992-12-15 At&T Bell Laboratories Molded circuit package having heat dissipating post
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