JPS62229961A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPS62229961A
JPS62229961A JP61071134A JP7113486A JPS62229961A JP S62229961 A JPS62229961 A JP S62229961A JP 61071134 A JP61071134 A JP 61071134A JP 7113486 A JP7113486 A JP 7113486A JP S62229961 A JPS62229961 A JP S62229961A
Authority
JP
Japan
Prior art keywords
resin
heat sink
semiconductor device
bed
mold layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61071134A
Other languages
Japanese (ja)
Other versions
JPH0680748B2 (en
Inventor
Toshihiro Kato
加藤　俊博
Shinjiro Kojima
小島　伸次郎
Takao Emoto
江本　孝朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61071134A priority Critical patent/JPH0680748B2/en
Priority to DE8686304725T priority patent/DE3684184D1/en
Priority to EP86304725A priority patent/EP0206771B1/en
Priority to KR1019860006424A priority patent/KR900001984B1/en
Publication of JPS62229961A publication Critical patent/JPS62229961A/en
Priority to US07/334,771 priority patent/US4924351A/en
Publication of JPH0680748B2 publication Critical patent/JPH0680748B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Abstract

PURPOSE:To improve the heat dissipation characteristics by increasing the contact space with a resin layer laid between a heat sink and a bed part by a method wherein, within a resin sealed semiconductor device composed of the bed part and the heat sink insulated from each other by means of laying resin for enclosure between them, the back surface of bed part is provided with recessions. CONSTITUTION:The back surface of a bed part 21 is formed into recessions 7 to increase the contact space with the second resin mold layer 62 improving the heat conductivity between the two elements 21 and 62. Likewise, the surface of heat sink l is formed into the other recessions 8 to increase the contact space with the second resin mold layer 62 improving the heat conductivity between the two elements 62 and l. Resultsntly, the heat resistance between the bed part 21 and the heat sink l is reduced to markedly improved the heat dissipation characteristics of a semiconductor device. Furthermore, the bed part 21 can increase the mechanical strength by forming the back surface thereof into multiple recessions 7.

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は樹脂封止型半導体装置に関し、特に半導体チッ
プに対して絶縁されたヒートシンクを有する樹脂封止型
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device having a heat sink insulated from a semiconductor chip.

（従来の技術） たとえば／？クワ−ランジスタアレイのような電力用半
導体装置では、１つのヒートシンク上に複数の半導体チ
ップをマウントして組立て、これを単一の樹脂モールド
層で封止した形態のものが知られている。このような半
導体装置では、当然ながら、個々の半導体チップとヒー
トシンクとは絶縁されていなければならない。このため
、当初はセラミック基板が用いられていたが、コストが
高いことや加工性に問題があることから５種々の代替案
が提案されている。(Conventional technology) For example/? 2. Description of the Related Art A power semiconductor device such as a quaran transistor array is known in which a plurality of semiconductor chips are mounted and assembled on one heat sink, and this is sealed with a single resin mold layer. Naturally, in such a semiconductor device, each semiconductor chip and a heat sink must be insulated. For this reason, ceramic substrates were initially used, but five different alternatives have been proposed due to their high cost and problems with workability.

本願出願人もセラミック基板を用いず、通常の金属製ヒ
ートシンクのみを用いて半導体テッグ相互間の絶縁を達
成し得る樹脂封止型半導体装置の構造を提案しておシ、
さらに、その改良案を特願昭６０−１３４６５８号によ
り提案している。即ち。The applicant of the present application has also proposed a structure of a resin-sealed semiconductor device that can achieve insulation between semiconductor tags using only an ordinary metal heat sink without using a ceramic substrate.
Furthermore, an improvement plan has been proposed in Japanese Patent Application No. 60-134658. That is.

この改良された樹脂封止型半導体装置は、金属製のベッ
ド部表面にマウントされた半導体チップと、前記ベッド
部および前記半導体チップを前記ベッド部の裏面が露出
するように封止する第１の樹脂モールド層と、前記ベッ
ド部の露出した裏面下に所定の距離を置いて配置された
金属製のヒートシンクおよび前記第１の樹脂モールド層
の外周側面を覆い、且つ前記ベッド部の裏面と前記ヒー
トシンクとの間の間隙に充填されて形成された第２の樹
脂モールド層と、この第２の樹脂モールド層を貫通して
その先端部が前記第１の樹脂モールド層内に配置され、
且つゲンディ／グワイヤを介して前記半導体チップ表面
の内部端子に接続されたリードとを具備したことを特徴
とするものである。This improved resin-sealed semiconductor device includes a semiconductor chip mounted on the surface of a metal bed part, and a first part that seals the bed part and the semiconductor chip so that the back surface of the bed part is exposed. a resin mold layer, a metal heat sink disposed at a predetermined distance below the exposed back surface of the bed section, and a metal heat sink that covers the outer peripheral side surface of the first resin mold layer, and that covers the back surface of the bed section and the heat sink. a second resin mold layer formed by filling a gap between the second resin mold layer and a tip thereof penetrating the second resin mold layer and disposed within the first resin mold layer;
The device is characterized in that it further includes a lead connected to an internal terminal on the surface of the semiconductor chip via a wire.

上記構造の半導体装置は、樹脂モールド層を二層に分け
たことを要点とするもので、第１の樹脂モールド層を形
成した後、第２の樹脂モールド層をトランスファモール
ドして製造することになる。The key point of the semiconductor device having the above structure is that the resin mold layer is divided into two layers, and after forming the first resin mold layer, the second resin mold layer is transfer molded to manufacture the semiconductor device. Become.

この場合、一段階のみのトランスファモールドによる従
来の場合とは溶融樹脂の流れが異なり、最終的に空気が
溜シ易い部分はベッド部とヒートシンクとの間の間隙で
はなく、第１の樹脂モールド層の外側部分になる。その
結果、第２の樹脂モールド層として粘度の高い樹脂を用
い、且つベッド部とヒートシンクとの間の間隙を狭くし
た場合にも、この間隙内を充填する樹脂層に？イドが形
成されるのを防止できる。従って、第２の樹脂モールド
層としてシリカ含有量の多い高熱伝導率の樹脂を用い、
絶縁性を維持しつつ放熱特性を向上することか可能とな
る。In this case, the flow of the molten resin is different from the conventional case using only one stage of transfer molding, and the area where air tends to accumulate is not the gap between the bed section and the heat sink, but the first resin mold layer. becomes the outer part of As a result, even when a highly viscous resin is used as the second resin mold layer and the gap between the bed section and the heat sink is narrowed, the resin layer filling the gap will have a large amount of viscosity. This can prevent the formation of id. Therefore, using a high thermal conductivity resin with a high silica content as the second resin mold layer,
It becomes possible to improve heat dissipation characteristics while maintaining insulation properties.

また、第２の樹脂モールド層を形成する際には、既に第
１の樹脂モールド層が形成されているから、高粘性の溶
融樹脂によるトランスファモールドに際してもゲンディ
／グオーグン等の問題は発生しない。Further, when forming the second resin mold layer, since the first resin mold layer has already been formed, problems such as gendy/googun do not occur even when transfer molding is performed using a highly viscous molten resin.

しかし、上記構造の半導体装置を試作して放熱特性を測
定したところ、必らずしも十分な特性が得られず、しか
もそのばらつきが大きいという問題があった。この原因
を究明した結果、ベッド裏面と第２のモールド層樹脂の
界面との間゛に僅か（数μｍ程度）のエアギャップ層が
形成されていることが判った。これは、使用するトラン
スファモールド樹脂と金属製ベッドとの接着力が十分で
ないことに起因しており、上記エアギャップ層の存在に
より熱伝導性が十分に得られないことが判った。However, when a semiconductor device having the above structure was prototyped and its heat dissipation characteristics were measured, there was a problem in that sufficient characteristics were not always obtained, and furthermore, the variation was large. As a result of investigating the cause of this, it was found that a slight air gap layer (about several μm) was formed between the back surface of the bed and the interface of the second mold layer resin. This is due to insufficient adhesion between the transfer mold resin used and the metal bed, and it was found that sufficient thermal conductivity could not be obtained due to the presence of the air gap layer.

（発明が解決しようとする問題点） 本発明は上記したように金属製ベッド部の裏面と樹脂モ
ールド層の界面との間の熱伝導性が十分に得られないと
いう問題点を解決すべくなされたもので、上記熱伝導性
を大幅に改善でき、半導体装置の放熱特性を大幅に改善
でき、しかも上記ベッド部の機械的強度を高め得る樹脂
封止型半導体装置を提供することを目的とする。(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned problem that sufficient thermal conductivity cannot be obtained between the back surface of the metal bed portion and the interface of the resin mold layer. It is an object of the present invention to provide a resin-sealed semiconductor device that can significantly improve the thermal conductivity, greatly improve the heat dissipation characteristics of the semiconductor device, and increase the mechanical strength of the bed portion. .

〔発明の構成コ （問題点を解決するための手段） 本発明は、金属製のベッド部上に半導体チップをマウン
トし、その表面の内部端子をゲンディングワイヤにより
てリードの先端部に接続し、これらを上記ベッド部の裏
面が露出するように第１の樹脂モールド層により封止し
、さらに上記ベッド部の裏面下に所定の間隔をあけて金
属製のヒートシンクが位置する配置で上記間隔部に充填
すると共に上記第１の樹脂モールド層の側面およびヒー
トシンクの側面ならびに前記リードの中間部を覆うよう
に第２の樹脂モールド層を形成してなることを特徴とす
る樹脂封止型半導体装置において、前記ベッド部の裏面
に凹部を形成してなることを特徴とするものである。[Structure of the Invention (Means for Solving the Problems)] The present invention mounts a semiconductor chip on a metal bed, and connects internal terminals on the surface of the chip to the tips of leads using ending wires. , these are sealed with a first resin mold layer so that the back surface of the bed section is exposed, and further, a metal heat sink is positioned below the back surface of the bed section at a predetermined interval, so that the gap section is sealed. In a resin molded semiconductor device, a second resin mold layer is formed to cover the side surfaces of the first resin mold layer, the side surfaces of the heat sink, and the intermediate portions of the leads. , a concave portion is formed on the back surface of the bed portion.

（作用） 前記したような二層モールド構造を実現する際、ベッド
部とヒートシンクとの間の間隙を狭くすると共に第２の
樹脂モールド層としてシリカ含有量の多い高熱伝導率の
ものを用いた場合でも上記間隙部にボイドが形成される
のを防止でき、絶縁性を維持しつつ放熱特性を向上する
ことが可能になる。　　− しかも、ベッド部の裏面は、凹部の存在によって第２の
樹脂モールド層との接触面積が大きくなっており、ベッ
ド部と第２の樹脂モールド層との間の熱伝導性が向上し
ている。したがって、ベッド部とヒートシンクとの間の
熱抵抗が小さくなり、放熱特性が大幅に改善される。(Function) When realizing the above-mentioned two-layer mold structure, the gap between the bed part and the heat sink is narrowed, and the second resin mold layer is made of a material with high thermal conductivity and high silica content. However, it is possible to prevent voids from being formed in the gap, and it is possible to improve heat dissipation characteristics while maintaining insulation properties. - Moreover, the contact area with the second resin mold layer on the back surface of the bed part is increased due to the presence of the recess, and the thermal conductivity between the bed part and the second resin mold layer is improved. . Therefore, the thermal resistance between the bed portion and the heat sink is reduced, and the heat dissipation characteristics are significantly improved.

（実施例） 以下、図面を参照して本発明の一実施例を詳細に説明す
る。第１図において、１はヒートシンクであってアルミ
ニウム板又は鋼板等の熱伝導性の高い金属板からなり、
その平面構造はたとえば第２図に示すようなものであっ
て放熱板（９示せず）に固着するためのビス止め孔１ノ
が形成されている。２１はリードフレーム２のベッド部
であって、上記リードフレーム２は銅系あるいは鉄系合
金等の導電性金属板がたとえば第３図に示すようにノ！
ターニングされて形成されたものである。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, 1 is a heat sink, which is made of a metal plate with high thermal conductivity such as an aluminum plate or a steel plate.
Its planar structure is, for example, as shown in FIG. 2, and has screw holes 1 for fixing it to a heat sink (9 not shown). 21 is a bed portion of the lead frame 2, and the lead frame 2 is made of a conductive metal plate made of copper or iron alloy, for example, as shown in FIG.
It is formed by turning.

上記リードフレーム２には、独立した４つのベッド部２
１・・・とリードノやターン部２２とが形成されており
、これらはフレーム部２３に連結されて支持されている
。上記ベッド部２１は、その大きさがたとえばＩＯＩＩ
ＬＸＩＯＩｍであり、その上には半田合金等のマウント
材層３により半導体チンｆ４がグイゲンディングされて
おり、このチップ４の表面上の内部端子はＡｕ　、　ｋ
Ｌ等の金属細線からなるボンディングワイヤ５により前
記リードパターン部２２の先端部との間で所要の電気的
接続が行なわれている。The lead frame 2 has four independent bed sections 2.
1 . . . and lead knots and turn portions 22 are formed, and these are connected to and supported by a frame portion 23. The size of the bed portion 21 is, for example, IOII.
A semiconductor chip f4 is mounted on it by a mounting material layer 3 such as a solder alloy, and internal terminals on the surface of this chip 4 are made of Au, k.
A required electrical connection is made with the tip of the lead pattern section 22 by a bonding wire 5 made of a thin metal wire such as L.

上記したベッド部２ノ、リード・リーン部２２の先端部
、マウント材層３、半導体チップ４、ボンディングワイ
ヤ５は、上記ベッド部２１の裏面が露出するように第１
の樹脂モールド層６１により封止されている。そして、
上記ベッド部２Ｉの裏面下に所定距離（たとえば０．３
　ｆｌ　）をおいて前記ヒートシンク１が配置されてお
り、これらの間の間隙を充填し、且つ上記第１の樹脂モ
ールド）ｆ１６１の側面およびヒートシンク１の側面な
らびに前記リードパターン部２２の中間部を覆うように
第２の樹脂モールドノー６１が形成されている。即ち、
樹脂モールド層６が二層構造になっており、各層５１＋
６２とも結晶性シリカを含む高熱伝導性エポキシ樹脂か
らなっている。この場合、第１の樹脂モールド層６１に
は、λ（熱伝導率）＝６０Ｘ１０　　ｅａｊ々・１Ｉｅ
ｃ・℃のものが用いられ、第２の樹脂モールド層６□に
は熱伝導率が一層高いλ＝８０〜９０Ｘ１０Ｃ＆ｔ／ｃ
ＩｒＬ・Ｈｌｅ・℃のものが用いられている。The bed portion 2, the tip of the lead/lean portion 22, the mounting material layer 3, the semiconductor chip 4, and the bonding wire 5 are placed in the first position so that the back surface of the bed portion 21 is exposed.
It is sealed with a resin mold layer 61. and,
A predetermined distance (for example, 0.3
The heat sink 1 is placed at a distance from the first resin mold (fl), and fills the gap between them, and covers the side surface of the first resin mold (f161), the side surface of the heat sink 1, and the intermediate portion of the lead pattern section 22. A second resin mold node 61 is formed as shown in FIG. That is,
The resin mold layer 6 has a two-layer structure, and each layer 51+
62 are both made of highly thermally conductive epoxy resin containing crystalline silica. In this case, the first resin mold layer 61 has λ (thermal conductivity)=60×10 eaj·1Ie
c・℃ is used, and the second resin mold layer 6□ has a higher thermal conductivity, λ=80~90X10C&t/c.
IrL・Hle・℃ is used.

さらに、前記ベッド部２１の裏面には複数の凹部７・・
・が散在して形成されておシ、前記ヒートシンク１の上
面にも複数の凹部８・・・が散在して形成されている。Further, on the back surface of the bed portion 21, there are a plurality of recesses 7...
* are formed in a scattered manner, and a plurality of recesses 8 are also formed in a scattered manner on the upper surface of the heat sink 1.

これらの凹部７・・・、８・・・は、ベッド部裏面、ヒ
ートン／り上面に対する機械的加工により予め形成され
ており、たとえばコイニング加工によシ凹部群が形成さ
れたのちホー二／グ加工により粗面化が行なわれる。こ
こで、コイニング加工による凹部群の平面形状の種々の
例を第４図（ａ）乃至（、）に示しており、同図（、）
は丸穴、同図（ｂ）は縦溝、同図（Ｃ）は行列状配列の
方形穴、同図（ｄ）は市松模様状配列の方形穴、同図（
ｅ）は三角穴である。These recesses 7..., 8... are formed in advance by mechanical processing on the back surface of the bed portion and the upper surface of the heat exchanger. The surface is roughened by processing. Here, various examples of the planar shape of the recess group by coining processing are shown in Fig. 4(a) to (,).
(b) is a vertical groove, (C) is a square hole arranged in a matrix, (d) is a square hole arranged in a checkered pattern, (
e) is a triangular hole.

なお、上記実施例の樹脂封止型半導体装置の製造に際し
ては、従来と同様にリードフレーム２上で半導体チッｆ
４のダイゲ／ディングおよびワイヤゲ／ディ／グを行な
った後、トランスファモールドにより第１の樹脂モール
ド層６１を形成して樹脂封止を行なう。次Ｋ、ヒートシ
ンク１をトランスファモールド金型内に設置し、上記樹
脂封止されたリードフレーム２を上記ヒートシンクＪの
上方に所定間隔をあけて配設し、この状態でトランスフ
ァモールドを行なって第２の樹脂モールド層６２を形成
する。この２回目のトランスファモールドにおいて、樹
脂液は、先ずヒートシンク１と第１の樹脂モールドｌ１
１６１との間を流れてから第１の樹脂モールド層６１の
外周側に流れ込む。したがって、この場合の空気の逃げ
場は第２の樹脂モールド層６２の形成空間であシ、ヒー
トシンク１と第１の樹脂モールド層６１との間の間隙部
分には同等ディトを生じることなく高熱伝導率の樹脂を
充填することが可能である。このように樹脂封止した後
にリードフォーミングを行なって得られた製品の正面外
観を第５図に示しており、そのＡ　−Ａ’線に沿う断面
構造は第１図に示した通りである。Incidentally, when manufacturing the resin-sealed semiconductor device of the above embodiment, the semiconductor chip f is placed on the lead frame 2 as in the conventional case.
After performing die/dying and wire gaging/dying in step 4, a first resin mold layer 61 is formed by transfer molding, and resin sealing is performed. Next, the heat sink 1 is installed in a transfer molding mold, the resin-sealed lead frame 2 is placed above the heat sink J at a predetermined interval, and transfer molding is performed in this state. A resin mold layer 62 is formed. In this second transfer molding, the resin liquid is first applied to the heat sink 1 and the first resin mold l1.
161 , and then flows to the outer peripheral side of the first resin mold layer 61 . Therefore, the place for air to escape in this case is the space where the second resin mold layer 62 is formed, and the gap between the heat sink 1 and the first resin mold layer 61 has high thermal conductivity without producing the same amount of heat. It is possible to fill with resin. FIG. 5 shows the front appearance of a product obtained by performing lead forming after resin sealing, and its cross-sectional structure along line AA' is as shown in FIG. 1.

上記実施例の樹脂封止型半導体装置によれば、ベッド部
２１は、その裏面に凹部７・・・が形成されているので
第２の樹脂モールド層６！との接触面積が大きくなって
おシ、上記両者２１　ｒ　６２間の熱伝導性が向上して
いる。同様に、ヒートシンク１も、その上面に凹部８・
・・が形成されていて第２の樹脂モールド層６２との接
触面積が大きくなっているので、上記両者６２．１間の
熱伝導性が向上している。According to the resin-sealed semiconductor device of the above embodiment, the bed portion 21 has the recesses 7 formed on its back surface, so that the second resin mold layer 6! The contact area between the two is increased, and the thermal conductivity between the two is improved. Similarly, the heat sink 1 also has a recess 8 on its top surface.
. . are formed and the contact area with the second resin mold layer 62 is increased, so that the thermal conductivity between the two 62.1 is improved.

したがって、ベッド部２ノとヒートシンクｌとの間の熱
抵抗Ｒｔｈは前述した提案例の構造のもの（凹部７・・
・、８・・・が形成されていないもの）に比べて大幅に
小さくなシ、半導体装置の放熱特性が大幅に改善されて
いる。しかも、ベッド部２ノは、その裏面に複数の凹部
７・・・が形成されていることによってその機械的強度
も扁くなっている。さらに、上記実施例の半導体装置は
、前述した提案例の構造のものに比べて前記凹部７・・
・、８・・・が形成されている点が異なるだけであり、
上記提案例の構造による特長を全て備えている。Therefore, the thermal resistance Rth between the bed part 2 and the heat sink l is the same as that of the structure of the proposed example described above (recessed part 7...
. Furthermore, the mechanical strength of the bed portion 2 is also reduced due to the plurality of recesses 7 formed on the back surface thereof. Furthermore, in the semiconductor device of the above embodiment, the recess 7...
The only difference is that . . , 8 . . . are formed,
It has all the features of the structure of the above proposed example.

なお、本発明は上記実施例に限らず、凹部７・・・。Note that the present invention is not limited to the above-mentioned embodiments, and the recessed portion 7...

１・・・がそれぞれコイニング加工のみ、あるいはホー
ニング加工のみ（ドライホーニングでもウェットホーニ
ングでもよい）によって形成された場合でも、ヒートシ
ンク上面には凹部８・・・が形成されることなくベッド
部裏面にのみ凹部７・・・が形成された場合でも前記実
施例と同質の効果が得られる。Even if 1... is formed only by coining processing or only by honing processing (dry honing or wet honing may be used), recesses 8... are not formed on the top surface of the heat sink and only on the back surface of the bed part. Even when the recesses 7 are formed, the same effects as in the embodiment described above can be obtained.

これらの各場合におけるベッド部、ヒートシンク間の熱
抵抗Ｒｔｈの実測データを下表に示す。ここで、（１）
は前述した提案例の構造のものに相当し、七のＲｔｈが
たとえば２．７℃／Ｗであり、（２）〜（５）は凹部群
の形成個所および形成方法の組み合わせが異なるもので
あって、その他の条件は上記（１）の構造のものと同じ
である。下表から、（５）の構造のもの（前記実施例に
相当する〕のＲｔｈは１．６℃／Ｗであって、（１）の
構造のものに比べて約０．６倍に小さくなっており、放
熱特性が約４０％改善されていることが分る。The table below shows the measured data of the thermal resistance Rth between the bed section and the heat sink in each of these cases. Here, (1)
corresponds to the structure of the proposed example described above, and the Rth of 7 is, for example, 2.7°C/W, and (2) to (5) have different combinations of the formation locations and formation methods of the recess group. The other conditions are the same as those for the structure (1) above. From the table below, the Rth of the structure (5) (corresponding to the above example) is 1.6°C/W, which is about 0.6 times smaller than that of the structure (1). It can be seen that the heat dissipation characteristics are improved by about 40%.

なお、上記（５）の実施例において、第２の樹脂モール
ド層６２として熱伝導率がさらに高いもの（たとえばλ
＝８５Ｘ１０　　ｃｍｌ／Ｃ１１１ｍ　ｓｅｃ　・１：
　）　ｆ用いることによって、熱抵抗Ｒｔｈを１．４℃
／Ｗ以下にすることができることが確認された。In the embodiment (5) above, the second resin mold layer 62 has a higher thermal conductivity (for example, λ
=85X10 cml/C111m sec ・1:
) By using f, the thermal resistance Rth can be reduced to 1.4℃.
It was confirmed that it is possible to reduce the power consumption to /W or less.

第６図はパワートランジスタプレイの一例トシてダーリ
ントン接続されたパワートランジスタ６０が６個設けら
れた回路を示しておシ、このようなパワートランジスタ
アレイに本発明を適用すれば、その放熱特性がよいこと
から他の条件（パッケージの大きさ等）が同一のままで
もその高出力化を実現できた。FIG. 6 shows an example of power transistor play, showing a circuit including six Darlington-connected power transistors 60. If the present invention is applied to such a power transistor array, its heat dissipation characteristics will be good. This made it possible to achieve high output even if other conditions (package size, etc.) remained the same.

また、本発明はノ臂ワートランジスタアレイに限らず、
ダイオードアレイ、ノぐワーソリッドステートリレー、
／４′ワーフォトカグラ等にも適用して効果的である。Furthermore, the present invention is not limited to arm transistor arrays;
Diode array, solid state relay,
/4' It is also effective when applied to war photo kagura, etc.

また、本発明は、複数個の半導体チップを単一のパッケ
ージ内に封止する場合に限らず、１個の半導体チップを
封止した半導体装置（パワートランジスタなど）にも適
用して効果的である。Furthermore, the present invention is effective not only when a plurality of semiconductor chips are sealed in a single package, but also when applied to a semiconductor device (such as a power transistor) where a single semiconductor chip is sealed. be.

［発明の効果コ 上述したように本発明によれば、ベッド部とヒートシン
クとの間に外囲器用の樹脂を介在させて両者間を絶縁し
た樹脂封止型半導体装置において、ベッド部とヒートシ
ンクとの間の距離を短縮すると共にボイドの発生を防止
し、且つ両者間に介在するモールド樹脂層の結晶性シリ
カ含有率を増大し、絶縁性を維持しつつ放熱特性を向上
させることが可能になる。しかも、前記ベッド部の裏面
に凹部を設けておくことによってヒートシンクとの間に
介在する樹脂層との接触面積を大きくしているので、ベ
ッド部とヒートシンクとの間の熱伝導率がよくなり、放
熱特性を一層改善することができるという顕著な効果が
得られる。[Effects of the Invention] As described above, according to the present invention, in a resin-sealed semiconductor device in which an envelope resin is interposed between the bed part and the heat sink to insulate the two, the bed part and the heat sink are It becomes possible to shorten the distance between the two, prevent the occurrence of voids, and increase the crystalline silica content of the molded resin layer interposed between the two, thereby improving heat dissipation characteristics while maintaining insulation properties. . Moreover, by providing a recess on the back surface of the bed section, the contact area with the resin layer interposed between the bed section and the heat sink is increased, so the thermal conductivity between the bed section and the heat sink is improved. A remarkable effect is obtained in that the heat dissipation characteristics can be further improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の樹脂封止型半導体装置の一実施例を示
す断面図、第２図は第１図中のヒートシンクの一例を示
す平面図、第３図は第１図中のリードフレームの一例を
示す平面図、第４図（ａ）乃至（、）は第１図中のベッ
ド部の裏面およびヒートシンクの上面に形成された凹部
の相異なる例を示す平面図、第５図は第１図の装置の外
ｆＩ！を示す正面図、第６図は第１図の装置の一適用例
であるパワートランノスタアレイの一例を示す回路図で
ある。 Ｊ・・・ヒートン／り、２・・・リードフレーム、２１
・・・ベッド部、２２・・・リードパターン部、４・・
・半４体チップ、５・・・デンディングワイヤ、６１・
・・第１のモールド樹脂層、６２・・・第２のモールド
樹脂層、７・・・凹部。 出願人代理人　　弁理士　鈴　江　武　彦第１図 第２図 第３図 （ａ）（ｂ） （ｃ　）　　　　　　　　　　（ｄ　）（ｅ） ΔΔΔ ΔΔ ヘヘヘ 第４図FIG. 1 is a cross-sectional view showing one embodiment of the resin-sealed semiconductor device of the present invention, FIG. 2 is a plan view showing an example of the heat sink in FIG. 1, and FIG. 3 is a lead frame in FIG. 1. 4(a) to 4(,) are plan views showing different examples of recesses formed on the back surface of the bed portion and the top surface of the heat sink in FIG. 1, and FIG. Outside fI of the device in Figure 1! FIG. 6 is a circuit diagram showing an example of a power transnoster array which is an application example of the device shown in FIG. J... Heaton/Ri, 2... Lead frame, 21
...Bed part, 22...Lead pattern part, 4...
・Half 4 body chip, 5...Dending wire, 61・
. . . first mold resin layer, 62 . . . second mold resin layer, 7 . . . recess. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 (a) (b) (c) (d) (e) ΔΔΔ ΔΔ Hehehe Figure 4

Claims (4)

【特許請求の範囲】[Claims] （１）裏面に凹部が形成された金属製のベッド部と、こ
のベッド部の表面上にマウントされた半導体チップと、
この半導体チップの内部端子にボンディングワイヤによ
り接続されたリードと、これらの半導体チップ、ベッド
部、ボンディングワイヤおよびリードの先端部をベッド
部裏面が露出するように封止する第１の樹脂モールド層
と、上記ベッド部の裏面下に所定距離の間隙をあけて配
設された金属製のヒートシンクと、このヒートシンクの
側面および前記第１の樹脂モールド層の側面ならびに前
記リードの中間部を覆い、且つ前記ベッド部の裏面とヒ
ートシンクの上面との間の間隙に充填されて形成された
第２の樹脂モールド層とを具備してなることを特徴とす
る樹脂封止型半導体装置。(1) A metal bed part with a recess formed on the back surface, a semiconductor chip mounted on the surface of this bed part,
Leads connected to internal terminals of the semiconductor chip by bonding wires, and a first resin mold layer that seals the semiconductor chip, the bed, the bonding wires, and the tips of the leads so that the back surface of the bed is exposed. , a metal heat sink disposed below the back surface of the bed part with a predetermined gap therebetween, and covering the side surface of the heat sink, the side surface of the first resin mold layer, and the intermediate portion of the lead; A resin-sealed semiconductor device comprising: a second resin mold layer formed by filling a gap between the back surface of the bed portion and the top surface of the heat sink. （２）前記ヒートシンクの上面にも凹部が形成されてい
ることを特徴とする前記特許請求の範囲第１項記載の樹
脂封止型半導体装置。(2) The resin-sealed semiconductor device according to claim 1, wherein a recess is also formed on the upper surface of the heat sink. （３）前記凹部は複数個散在して形成されていることを
特徴とする前記特許請求の範囲第１項または第２項記載
の樹脂封止型半導体装置。(3) The resin-sealed semiconductor device according to claim 1 or 2, wherein a plurality of the recesses are formed in a scattered manner. （４）前記凹部はコイニング加工およびまたはホーニン
グ加工により形成されてなることを特徴とする前記特許
請求の範囲第３項記載の樹脂封止型半導体装置。(4) The resin-sealed semiconductor device according to claim 3, wherein the recess is formed by coining processing and/or honing processing.
JP61071134A 1985-06-20 1986-03-31 Resin-sealed semiconductor device Expired - Fee Related JPH0680748B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP61071134A JPH0680748B2 (en) 1986-03-31 1986-03-31 Resin-sealed semiconductor device
DE8686304725T DE3684184D1 (en) 1985-06-20 1986-06-19 ENCLOSED SEMICONDUCTOR ARRANGEMENT.
EP86304725A EP0206771B1 (en) 1985-06-20 1986-06-19 Packaged semiconductor device
KR1019860006424A KR900001984B1 (en) 1986-03-31 1986-08-04 Rasin sealing type semiconductor device
US07/334,771 US4924351A (en) 1985-06-20 1989-04-10 Recessed thermally conductive packaged semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61071134A JPH0680748B2 (en) 1986-03-31 1986-03-31 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPS62229961A true JPS62229961A (en) 1987-10-08
JPH0680748B2 JPH0680748B2 (en) 1994-10-12

Family

ID=13451801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61071134A Expired - Fee Related JPH0680748B2 (en) 1985-06-20 1986-03-31 Resin-sealed semiconductor device

Country Status (2)

Country Link
JP (1) JPH0680748B2 (en)
KR (1) KR900001984B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0366150A (en) * 1989-08-03 1991-03-20 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH07169882A (en) * 1991-05-23 1995-07-04 At & T Corp Molded integrated circuit package
JP2011258814A (en) * 2010-06-10 2011-12-22 Toyota Motor Corp Semiconductor device cooler
JP2012195497A (en) * 2011-03-17 2012-10-11 Sumitomo Electric Ind Ltd Semiconductor device and manufacturing method of the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002166A (en) * 1996-11-28 1999-12-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP3910144B2 (en) * 2003-01-06 2007-04-25 シャープ株式会社 Semiconductor light emitting device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211761A (en) * 1981-06-23 1982-12-25 Nec Corp Semiconductor device
JPS58151035A (en) * 1982-03-04 1983-09-08 Toshiba Corp Preparation of semiconductor device
JPS58153355A (en) * 1982-03-08 1983-09-12 Toshiba Corp Resin sealed semiconductor device
JPS6139555A (en) * 1984-07-31 1986-02-25 Toshiba Corp Resin sealed type semiconductor device with heat sink

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211761A (en) * 1981-06-23 1982-12-25 Nec Corp Semiconductor device
JPS58151035A (en) * 1982-03-04 1983-09-08 Toshiba Corp Preparation of semiconductor device
JPS58153355A (en) * 1982-03-08 1983-09-12 Toshiba Corp Resin sealed semiconductor device
JPS6139555A (en) * 1984-07-31 1986-02-25 Toshiba Corp Resin sealed type semiconductor device with heat sink

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0366150A (en) * 1989-08-03 1991-03-20 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH07169882A (en) * 1991-05-23 1995-07-04 At & T Corp Molded integrated circuit package
JP2011258814A (en) * 2010-06-10 2011-12-22 Toyota Motor Corp Semiconductor device cooler
JP2012195497A (en) * 2011-03-17 2012-10-11 Sumitomo Electric Ind Ltd Semiconductor device and manufacturing method of the same
EP2688098A1 (en) * 2011-03-17 2014-01-22 Sumitomo Electric Industries, Ltd. Semiconductor device and method for manufacturing semiconductor device
EP2688098A4 (en) * 2011-03-17 2014-07-30 Sumitomo Electric Industries Semiconductor device and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
KR870009453A (en) 1987-10-26
KR900001984B1 (en) 1990-03-30
JPH0680748B2 (en) 1994-10-12

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