KR900000995B1 - 테스트 데이타 부하 기능을 갖춘 논리회로 - Google Patents
테스트 데이타 부하 기능을 갖춘 논리회로 Download PDFInfo
- Publication number
- KR900000995B1 KR900000995B1 KR1019860003366A KR860003366A KR900000995B1 KR 900000995 B1 KR900000995 B1 KR 900000995B1 KR 1019860003366 A KR1019860003366 A KR 1019860003366A KR 860003366 A KR860003366 A KR 860003366A KR 900000995 B1 KR900000995 B1 KR 900000995B1
- Authority
- KR
- South Korea
- Prior art keywords
- logic circuit
- input
- terminal
- output
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Tests Of Electronic Circuits (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP94856 | 1985-05-02 | ||
| JP60-94856 | 1985-05-02 | ||
| JP60094856A JPS61253918A (ja) | 1985-05-02 | 1985-05-02 | 論理回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR860009550A KR860009550A (ko) | 1986-12-23 |
| KR900000995B1 true KR900000995B1 (ko) | 1990-02-23 |
Family
ID=14121672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019860003366A Expired KR900000995B1 (ko) | 1985-05-02 | 1986-04-30 | 테스트 데이타 부하 기능을 갖춘 논리회로 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4736395A (https=) |
| EP (1) | EP0201287B1 (https=) |
| JP (1) | JPS61253918A (https=) |
| KR (1) | KR900000995B1 (https=) |
| DE (1) | DE3684955D1 (https=) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2659095B2 (ja) * | 1987-06-30 | 1997-09-30 | 富士通株式会社 | ゲートアレイ及びメモリを有する半導体集積回路装置 |
| US4860325A (en) * | 1988-06-24 | 1989-08-22 | Advanced Micro Devices, Inc. | Counter tester |
| US4979193A (en) * | 1989-04-26 | 1990-12-18 | Advanced Micro Devices, Inc. | Method and apparatus for testing a binary counter |
| JP2632731B2 (ja) * | 1989-08-02 | 1997-07-23 | 三菱電機株式会社 | 集積回路装置 |
| US5185769A (en) * | 1991-10-15 | 1993-02-09 | Acer Incorporated | Easily testable high speed digital counter |
| EP0541840B1 (en) * | 1991-11-11 | 1993-07-14 | Hewlett-Packard GmbH | Formatter circuit |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3458825A (en) * | 1966-02-17 | 1969-07-29 | Philips Corp | Bistable trigger circuit comprising two relatively complementary outputs and two inputs and a clock pulse input |
| DE1255715B (de) * | 1966-08-12 | 1967-12-07 | Philips Patentverwaltung | Bistabile Kippstufe mit mehr als zwei verschiedenartigen Bedingungs-Eingaengen |
| DE1537298B2 (de) * | 1967-10-21 | 1975-06-12 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Bistabile Kippstufe mit Vielfacheingängen |
| US3878405A (en) * | 1972-07-13 | 1975-04-15 | Teradyne Inc | Switching circuitry for logical testing of network connections |
| US4001553A (en) * | 1975-09-17 | 1977-01-04 | Rockwell International Corporation | Counter arrangement and associated test circuit for an electronic timing device |
| GB2030807B (en) * | 1978-10-02 | 1982-11-10 | Ibm | Latch circuit |
| JPS5668033A (en) * | 1979-11-09 | 1981-06-08 | Fujitsu Ltd | Logic circuit |
| JPS609221A (ja) * | 1983-06-28 | 1985-01-18 | Sharp Corp | テスト機能付分周回路 |
| US4627085A (en) * | 1984-06-29 | 1986-12-02 | Applied Micro Circuits Corporation | Flip-flop control circuit |
-
1985
- 1985-05-02 JP JP60094856A patent/JPS61253918A/ja active Granted
-
1986
- 1986-04-29 US US06/857,016 patent/US4736395A/en not_active Expired - Fee Related
- 1986-04-30 KR KR1019860003366A patent/KR900000995B1/ko not_active Expired
- 1986-05-01 EP EP86303323A patent/EP0201287B1/en not_active Expired - Lifetime
- 1986-05-01 DE DE8686303323T patent/DE3684955D1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0201287A2 (en) | 1986-11-12 |
| EP0201287B1 (en) | 1992-04-22 |
| EP0201287A3 (en) | 1989-06-14 |
| US4736395A (en) | 1988-04-05 |
| JPH0317413B2 (https=) | 1991-03-08 |
| KR860009550A (ko) | 1986-12-23 |
| DE3684955D1 (de) | 1992-05-27 |
| JPS61253918A (ja) | 1986-11-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4995039A (en) | Circuit for transparent scan path testing of integrated circuit devices | |
| US5406216A (en) | Technique and method for asynchronous scan design | |
| US5418407A (en) | Asynchronous to synchronous particularly CMOS synchronizers | |
| US4649539A (en) | Apparatus providing improved diagnosability | |
| US5025174A (en) | Flip-flop circuit | |
| JPH07504076A (ja) | 2重エッジトリガ型メモリー装置及びシステム | |
| US7231569B2 (en) | Scan flip-flop circuit with reduced power consumption | |
| EP0631391B1 (en) | Decoded counter with error check and self-correction | |
| US6445235B1 (en) | Iddq-testable uni-directional master-slave | |
| KR900000995B1 (ko) | 테스트 데이타 부하 기능을 갖춘 논리회로 | |
| US5068881A (en) | Scannable register with delay test capability | |
| US5132993A (en) | Shift register circuit | |
| US4672647A (en) | Serial data transfer circuits for delayed output | |
| KR960701539A (ko) | 단일 단자 펄스 게이팅 회로(single-ended pulse gating circuit) | |
| EP0147103B1 (en) | Mos implementation of shift register latch | |
| US5361289A (en) | Synchronous counter circuit having a plurality of cascade-connected counters | |
| US4771187A (en) | Bistable circuit | |
| US4680485A (en) | Quad-state control signal input circuit | |
| JPH0311125B2 (https=) | ||
| KR100245080B1 (ko) | 디 플립-플롭 회로 | |
| KR200252001Y1 (ko) | 업/다운 전환 카운터 | |
| KR0183752B1 (ko) | 지연회로를 구비한 출력포트 장치 | |
| JP2533946B2 (ja) | 集積回路 | |
| JPH05273314A (ja) | 半導体論理集積回路 | |
| KR19990085230A (ko) | 플립플롭 구동회로 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| G160 | Decision to publish patent application | ||
| PG1605 | Publication of application before grant of patent |
St.27 status event code: A-2-2-Q10-Q13-nap-PG1605 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U11-oth-PR1002 Fee payment year number: 1 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 7 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 19980217 Year of fee payment: 9 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 9 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 19990224 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-5-5-R10-R18-oth-X000 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-5-5-R10-R18-oth-X000 |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 19990224 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |