KR900000769Y1 - Auto-switching circuits of ntsc/pal systems for video casette player - Google Patents

Abstract

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Description

NTSC / PAL type automatic switching circuit of video cassette player

The accompanying drawings show the circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

10: servo control 20: switching control signal generator

30: monostable multivibrator 40: clock generator power supply

FFL ₁ , FF ₂ : Flip-flop 50: Clock generator

OP ₁ -OP ₄ : Comparator Q ₁ -Q ₈ : Transistor

C ₁ -C ₃ condenser X ₁ , X ₂ : oscillation element

R ₁ -R ₂ : resistance

The present invention relates to a video cassette player capable of compatible playback between NTSC broadcasting and PAL broadcasting.

In a conventional video cassette player, video tapes recorded by NTSC broadcasting are recorded in PAL broadcasting, and video tapes recorded by PAL broadcasting are not compatible with each other when playing video tapes recorded by NTSC broadcasting and PAL broadcasting. The video cassette player could not be played on NTSC broadcasting video cassette player. Especially, in Latin America where NTSC broadcasting and PAL broadcasting can be received at the same time, the video cassette player which can use the video tape recorded by the above two broadcasting methods can be used. Needed.

The present invention devised in view of the above-mentioned points, and the generation circuit of 3.579545MHz which is the servo control reference clock signal of NTSC broadcasting video cassette player and 4.435571MHz which is the servo control reference clock signal of PAL broadcasting video cassette player Each of them is configured to generate NTSC / PAT automatic switching voltage using the drum phase pulse width modulated signal and camston phase pulse width modulated signal generated in the conventional servo control integrated circuit and broadcast to the conventional servo control integrated circuit. It is an object of the present invention to provide a video cassette player circuit capable of compatible playback control of both broadcasting systems by applying a reference clock signal suitable for a system.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The accompanying drawings are circuit diagrams of the present design, which include a conventional servo controller 10, a switching control signal generator 20 for generating a control signal when the broadcasting system changes, a monostable multivibration 30, and a clock generation power supply. It is comprised as the application part 40 and the clock generation part 50. As shown in FIG.

The servo controller 10 may include a servo error control circuit 1 and a drum error voltage generation comparator OP ₁ comparing the speed and phase of the drum output from the servo control integrated circuit ₁ and the comparator OP. The output signal of the drum motor driver 2 and the drum motor 3 controlled by the output signal of ₄ ), the capstan ether voltage generation comparator OP ₃ for comparing the speed and phase of the capstan, and the comparator PP ₃ It is a conventional servo control circuit including a caps surface motor drive unit 4 and a capstan motor 5 controlled by the switch control signal generator 20 includes transistors Q ₁ -Q ₃ and a capacitor C _1. , C ₂ ) and a resistor (R ₄ -R ₇ ) to generate a control signal so that the broadcast method is switched in the device by the authorization signal from the servo control unit 10, the monostable multivibrator 30 the resistance (R4 ₄₅ -R ₂₂₎ and a comparator (OP _1, OP ₂₎ and the flip-flop (FF ₂₎ consists of a clock powered section 40 Lip-flop (FF1), and applying the output to the clock terminal a clock signal, a clock generator power applying unit 40 is a flip-flop (FF ₁₎ and the arc (R ₁₂ -R ₁₇₎ and a transistor (Q ₇ -Q ₈₎ It is configured to apply the power (B ⁺ ) to the clock generator 50, the clock generator 50 is a resistor (R _12- R ₁₇ ) and the transistor (Q _7- Q ₈ ) oscillation element (X ₁ , X ₂ ) a clock signal as a clock terminal of the servo control integrated circuit 1 of the servo controller 10 by operating one of the two clock regeneration circuits according to the applied power of the clock generator power applying unit 40. Will be applied.

Referring to the circuit operation of the present invention in detail according to the flow of the signal, first, when the power supply B ^- is applied to the circuit, the clock input terminal of the servo control integrated circuit 1 generates the clock as the servo control reference clock signal. the unit 3.579MH _Z or clock sinhojung of 4.435571MHz occurred in 50 becomes is applied to any one, which is in accordance with the state of the flip-peulreup (FF ₁₎ of the clock generator powered section 40 transistors (Q _5, Q ₆ ) is determined by operation.

In the initial state, when the clock frequency and the clock frequency recorded on the reproduced video tape coincide, the drum output pulses having the same DC voltage level and the opposite phase are modulated and the capstan phase pulse width modulated output is the resistance (R ₁ ). Since the transistor Q ₁ is synthesized through the over-resistance R ₂ , the base voltage of the transistor Q ₁ becomes 0, and the transistor Q ₁ does not operate.

However, when the clock frequency applied to the servo control integrated circuit 1 and the clock frequency recorded on the video tape to be reproduced do not match, the drum phase pulse width modulation output and the capstan phase pulse width modulation of the servo control integrated circuit 1 do not match. output is the irregular change from the high level to the low level, and the transistor (Q ₁₎ base bias resistor is to occur a change in the voltage on the (R _1, R ₂₎ of, when a high voltage to the transistor base is a transistor (Q ₁₎ Is turned on.

At this time, the transistor (Q ₁₎ each time that turns on the AC coupling capacitors (C _1, C ₂₎ is applied to the base of the DC voltage changes minutes transistor (Q _2, Q ₃₎ through the transistor (Q _2, Q ₃₎ It turns on and the output signals of the transistors Q ₂ and Q ₃ are applied to the monostable multivibrator 30 and charged to the capacitor C ₃ through the resistors R _{18 and} R 19. The one capacitor (C ₃₎ a voltage comparator (OP _1, OP ₂₎ resistors (R ₂₀ from the inverting terminal of the power source (B ⁺⁾ of the non-inverted and the common input to janja comparator (OP _1, OP ₂₎ for filling the , The voltage divided by R ₂₂ ) is applied, and the comparator OP ₂ is equal to or higher than the reference voltage (one-third of the circuit power supply B ⁺ ) set in the inverting terminal. output, and a comparator (OP _1), the reference voltage is set to an inverting ^terminal and a non-inverting terminal voltage when the above (hoerong power voltage of 2/3 B) is applied, and outputs a high level signal, the one that Gyoki (OP ₁₎ When the high level signal is outputted, the transistor Q ₄ is turned on so that the charging voltage of the capacitor C ₃ is discharged through the collector of the resistor R ₁₉ transistor Q ₄ , at which time the output of the flip-flop FF ₂ is output. Changes from high level to low level.

As described above, when the output signal of the flip-flop (FF ₂ ) generated by the charging voltage is applied to the capacitor of the flip-flop (FF ₁ ) to the capacitor C ₃ , the clock input signal goes from the high level to the low level. by by the output Q terminal and the Q terminal is inverted each other signal of the flip-flop (FF ₁₎ to vary the moment transistor (Q _5, Q ₀₎ on and off to, in the clock generating section 50 that generates a clock to date Power is cut off from the clock generation circuit and power is applied to the other clock generation circuit to start oscillation, and the oscillation signal is applied to the clock terminal of the servo control integrated circuit 1. At this time, the oscillation elements X ₁ and X ₂ are 3.479545 MHz, which is an NTSC reference clock signal and 4.535571 MHz, which is a PAL reference clock signal, respectively, and bias resistors R ₁₂ , R _13, and R of each transistor Q ₇ and Q ₈ . ₁₅ , R ₁₆ ) is automatically oscillated to generate a clock signal.

As described above, according to the present invention, a video tape recorded using either the NTSC broadcast method or the PAL broadcast method using a capstan phase pulse width modulated signal of the drum phase pulse width modulated signal output from the servo control integrated circuit 1 is used. It is possible to provide an NTSC / PAL type automatic switching circuit of a video cassette player capable of compatible playback even if playback is performed.

Claims (1)

In a servo control circuit of a video cassette player having a servo control integrated circuit, a voltage change between the drum whiskey pulse width modulation output and the capstan phase pulse width modulation output of the servo control integrated circuit 1 is detected to generate a control signal. By a signal applied from the clock generation section monostable multivibrator 30 and the monostable multivibrator 30 by the signal of the switching control signal generation section 20 and the switching control signal generation section 20 generated. The clock generator 50 generates a clock generator power supply unit 40 for supplying one of the two pulse generator circuits, and the NTSCP or PLT method reference clock signal to generate the servo control integrated circuit 1. A video cassette player NTSC / PAL type automatic switching circuit comprising a clock generator (50) applied to a clock terminal.