KR890017947A - Mosaic Screen Generation Circuit and Method of TV or Video Tape Recorder - Google Patents

Abstract

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Description

Mosaic Screen Generation Circuit and Method of TV or Video Tape Recorder

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1 is a circuit diagram of the present invention.

Claims (2)

A color difference separator, a frequency divider circuit, a synchronization separator, a color synthesizer, a keyboard 10 for generating a function selection signal for a function selected by the viewer, and a function selection signal for the keyboard 10 A television or video tape recorder having a microcomputer 20 for controlling the whole and an AD converter 30 for converting an analog chrominance signal into a digital signal of a first predetermined bit n from a switching control signal generator. Analog switch SW1 for sequentially transmitting the Y, RY, BY signals, which are color difference signals of the color difference separation circuit, to the AD converter 30 by the switching control signal applied, and the AD converter 30. The first data converter 40 converts the output into digital data of the second predetermined bit L and outputs the data at the fourth predetermined period, and the output of the first data converter 40 is input to the first port and stored. And the seventh prescribed Inputting the output of the second port of the dual port memory 50 and the dual port memory 50 for repeatedly reading out the above data amount and outputting the read data through the second port in a second predetermined bit unit A second data converter 41 for converting the first predetermined bit n into digital data and then outputting the data at a fifth predetermined cycle or sequentially outputting the first and third output ports at the sixth predetermined cycle, and the microcomputer 20. Decodes and decodes the mosaic control signal applied from the first clock and the ninth predetermined frequency (bfsc) of the eighth predetermined frequency (afsc) applied from the clock divider according to the horizontal and vertical synchronization signals applied from the synchronization separator. Reading the first and second latch signals and the seventh predetermined unit data amount of the dual port memory 50 to control the output period of the first and second digital converters 40 and 41 by dividing two clocks. To control the cycle The transmission control signal and a read (Read) / light bar (Write) signal, and controls for generating the read clock and the address and the address control signal decoder 60, the decoder control section 60 And inputting a read clock and an address and an address control signal to repeatedly read the seventh predetermined amount of data by the address control signal, and apply an address to the dual port memory 50 so that the data can be stored sequentially. With lead clock to control output simultaneously 1D-A for converting the digital Y signal output of the first output port of the second data converter 41 and the analog Y signal to the color combining unit A converter 80, a second D-A converter 81 for converting the digital RY signal output of the second output port of the second digital converter 41 into an analog RY signal and outputting the analog RY signal to the color combining unit; And a 3D-A converter (82) for converting the digital BY signal output of the third output port of the digital converter (41) into an analog BY signal and outputting it to the color synthesizer. In a television or video tape recorder, a Y, RY, BY signal, which is an analog color difference signal, is converted into a digital signal of a first predetermined bit (n) in the order of RY, Y, Y, BY, Y, Y, and then the second A data storage process of converting a predetermined bit L and storing the same in a memory; and performing a seventh predetermined unit digital signal corresponding to one horizontal scanning period of a random number in units of one horizontal scanning period during the data storage process. A plurality of dots for digital data corresponding to one dot data of random data by converting the data read-out process repeatedly read from the data and the data read by the data reading process into a first predetermined bit of data. And a data output process of converting and outputting the analog color difference signals Y, RY, and BY at the sixth predetermined period. ※ Note: The disclosure is based on the initial application.