KR890005842A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR890005842A
KR890005842A KR870010933A KR870010933A KR890005842A KR 890005842 A KR890005842 A KR 890005842A KR 870010933 A KR870010933 A KR 870010933A KR 870010933 A KR870010933 A KR 870010933A KR 890005842 A KR890005842 A KR 890005842A
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KR
South Korea
Prior art keywords
forming
electrode
planarization
manufacturing
photoresist mask
Prior art date
Application number
KR870010933A
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Korean (ko)
Inventor
박한수
김영희
한민석
Original Assignee
강진구
삼성반도체통신 주식회사
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Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR870010933A priority Critical patent/KR890005842A/en
Publication of KR890005842A publication Critical patent/KR890005842A/en

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Abstract

내용 없음No content

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2(A)-(D)도는 본 발명에 따른 사진 공정도.2 (A)-(D) are photographic process diagrams according to the present invention.

Claims (3)

반도체 장치의 제조방법에 있어서, 반도체기판상의 절연막(11)상부에 상기 반도체 기판에 형성된 소자의 소정부분과 접속을 하기 위한 전극물질층(12)을 도포하고 상기 전극물질층(12)상에 평탄화물질(13)을 형성한 후 상기 평탄화물질(13)상에 전극 형성을 위한 포토레지스트 마스크(14)를 형성하는 제 1공정과, 상기평탄화 물질(13)을 소정 에너지의 빛으로 노광하여 감광된 평탄화 물질을 제거하는 제 2공정과, 상기 포토레지스트 마스크(14)를 에칭마스크로 하여 상기 현상된 영역(5)하부의 평탄화 물질을 제거하는 제 3공정과, 상기 전극 물질층을 에칭하고 평탄화 물질(13)과 포토레지스트 마스크(14)를 제거하여 전극 패턴을 형성하는 제 4공정을 구비하여 상기 공정의 연속으로 이루어짐을 특징으로 하는 반도체 장치의 제조방법.In the method of manufacturing a semiconductor device, an electrode material layer 12 for applying connection with a predetermined portion of an element formed on the semiconductor substrate is coated on an insulating film 11 on a semiconductor substrate and planarized on the electrode material layer 12. Forming a photoresist mask 14 for forming an electrode on the planarization material 13 after forming the material 13, and exposing the planarization material 13 to light having a predetermined energy. A second process of removing the planarization material, a third process of removing the planarization material under the developed region 5 by using the photoresist mask 14 as an etching mask, and etching the planarization material by etching the electrode material layer And a fourth step of forming the electrode pattern by removing the photoresist mask (13) and the photoresist mask (14). 제 1항에 있어서, 평탄화 물질은 300nm이하의 파장을 갖는 빛에 의해서만 감광되는 유동성을 갖는 유기물질임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the planarization material is an organic material having fluidity which is exposed only by light having a wavelength of 300 nm or less. 제 1항에 있어서, 상기 제 2공정에서 200-500mJ/㎠의 에너지를 갖는 빛에 평탄화 물질을 노광함을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the planarizing material is exposed to light having an energy of 200-500 mJ / cm 2 in the second step. ※ 참고사항 : 최초 출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed by the contents of the original application.
KR870010933A 1987-09-30 1987-09-30 Manufacturing Method of Semiconductor Device KR890005842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR870010933A KR890005842A (en) 1987-09-30 1987-09-30 Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR870010933A KR890005842A (en) 1987-09-30 1987-09-30 Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR890005842A true KR890005842A (en) 1989-05-17

Family

ID=68343905

Family Applications (1)

Application Number Title Priority Date Filing Date
KR870010933A KR890005842A (en) 1987-09-30 1987-09-30 Manufacturing Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR890005842A (en)

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